Memory device sampling data using control signal transmitted through TSV

Patent metadata

Field	Value
Publication number	US-10740033-B2
Application number	US-201816197877-A
Country	US
Kind code	B2
Filing date	Nov 21, 2018
Priority date	Mar 30, 2018
Publication date	Aug 11, 2020
Grant date	Aug 11, 2020

Abstract

A memory die of a memory device includes a first first-in first-out (FIFO) circuit that samples data output from a memory cell array and outputs the data to a buffer die through a first through silicon via, based on a control signal transmitted from the buffer die. A buffer die of the memory device includes a second FIFO circuit that samples the data output from the first FIFO unit based on the control signal transmitted from the memory die through a second through silicon via, a calibration circuit that generates a delay code, based on a latency of a path from the buffer die to the first FIFO circuit and from the first FIFO circuit to the second FIFO circuit, and a delay control circuit that generates the control signal transmitted to the memory die through a third through silicon via, based on the read command and the delay code.

First claim

What is claimed is:

1. A memory device comprising:
a buffer die configured to receive a read command; and
a memory die configured to receive the read command transmitted from the buffer die,
wherein the memory die includes:
a memory cell array configured to output data in response to the read command; and
a first first-in first-out (FIFO) circuit configured to sample the data output from the memory cell array, and to output the data to the buffer die through a first through silicon via based on a control signal transmitted from the buffer die, and wherein the buffer die includes:
a second FIFO circuit configured to sample the data output from the first FIFO circuit through the first through silicon via, based on the control signal transmitted from the memory die through a second through silicon via;
a calibration circuit configured to generate a delay code, based on a latency of a path from the buffer die to the first FIFO circuit and from the first FIFO circuit to the second FIFO circuit; and
a delay control circuit configured to generate the control signal to be transmitted to the memory die through a third through silicon via, based on the read command and the delay code.

2. The memory device of claim 1 , wherein a depth of the second FIFO circuit indicating a number of bits of the data stored in the second FIFO circuit is smaller than a depth of the first FIFO circuit indicating a number of bits of the data stored in the first FIFO circuit.

3. The memory device of claim 2 , wherein the calibration circuit is further configured to count the latency of the path including the third through silicon via and including one of the first through silicon via and the second through silicon via.

4. The memory device of claim 2 , wherein the calibration circuit includes:
a counter configured to count a delay of a clock signal transmitted through the path in a measurement mode; and
a subtractor configured to calculate the delay code by subtracting a counting value of the counter from a value indicating a predetermined latency,
wherein the delay code corresponds to the depth of the first FIFO circuit and the counting value corresponds to the depth of the second FIFO circuit.

5. The memory device of claim 4 , wherein the buffer die further includes:
a command decoder configured to decode the read command and generate an internal read signal, and
wherein the delay control circuit is further configured to generate the control signal by delaying the internal read signal based on the delay code.

6. The memory device of claim 5 , wherein the delay control circuit does not delay the clock signal based on the delay code in the measurement mode, and delays the internal read signal based on the delay code when the buffer die receives the read command.

7. The memory device of claim 5 , wherein the memory die is a first memory die, the first memory die further including:
a first command decoder configured to decode the read command; and
a first delay control circuit configured to generate a first control signal under control of the first command decoder,
wherein the first FIFO circuit is configured to sample first data, which are the data output from a first memory cell array being the memory cell array, based on the first control signal,
wherein the command decoder of the buffer die is a second command decoder, and
wherein the delay control circuit of the buffer die is a second delay control circuit configured to generate a second control signal being the control signal.

8. The memory device of claim 7 , further comprising:
a second memory die stacked on the first memory die,
wherein the second memory die includes:
a second memory cell array configured to output second data in response to the read command;
a third command decoder configured to decode the read command;
a third delay control circuit configured to generate a third control signal under control of the third command decoder; and
a third FIFO circuit configured to sample the second data output from the second memory cell array, based on the third control signal and to output the second data to the buffer die through at least one fourth through silicon via and the first through silicon via, based on a fourth control signal transmitted from the buffer die,

wherein the second FIFO circuit of the buffer die is further configured to sample the second data output from the third FIFO circuit through the at least one fourth through silicon via and the first through silicon via, based on the fourth control signal transmitted from the second memory die through at least one fifth through silicon via,
wherein the buffer die generates a first clock, which is the clock signal passing through a first path being the path in the measurement mode, and generates a second clock signal passing through a second path from the buffer die to the third FIFO circuit and from the third FIFO circuit to the second FIFO circuit, and
wherein the calibration circuit is further configured to generate the delay code, based on a further delayed signal of clock signals passing through the first and second paths.

9. The memory device of claim 8 , wherein the first memory die further includes:
a first compare circuit configured to count a further delayed control signal of the first and third control signals and generate a first delay code,
wherein the delay code generated by the calibration circuit of the buffer die is a second delay code, and
wherein the second memory die further includes a second compare circuit configured to count a further delayed control signal of the first and third control signals and generate a third delay code.

10. The memory device of claim 9 , wherein the calibration circuit is further configured to adjust a first time point, at which the first data are output from the first FIFO circuit of the first memory die, and a second time point, at which the second data are output from the third FIFO circuit of the second memory die, so as to be identical to each other, by using the first and third delay codes.

11. A memory device comprising:
a buffer die configured to receive a read command; and
a memory die configured to receive the read command transmitted from the buffer die,
wherein the memory die includes:
a memory cell array configured to output data in response to the read command;
a delay control circuit configured to generate a control signal, based on the read command and a delay code output from the buffer die; and
a first first-in first-out (FIFO) circuit configured to sample the data output from the memory cell array, and to output the data to the buffer die through a first through silicon via based on the control signal, and

wherein the buffer die includes:
a second FIFO circuit configured to sample the data output from the first FIFO circuit through the first through silicon via, based on the control signal transmitted from the memory die through a second through silicon via; and
a calibration circuit configured to generate the delay code based on a latency of a path from the buffer die to the first FIFO circuit and from the first FIFO circuit to the second FIFO circuit.

12. The memory device of claim 11 , wherein a depth of the second FIFO circuit indicating a number of bits of the data stored in the second FIFO circuit is smaller than a depth of the first FIFO circuit indicating a number of bits of the data stored in the first FIFO circuit.

13. The memory device of claim 12 , wherein the memory die is a first memory die, the first memory die further including:
a first command decoder configured to decode the read command; and
a first delay control circuit config

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim So-Young
• Oh Reum
• Lee Haesuk

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title