Regulation of memory IO timing using programmatic control over memory device IO timing

US8930740B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8930740-B2
Application numberUS-94775810-A
CountryUS
Kind codeB2
Filing dateNov 16, 2010
Priority dateFeb 23, 2010
Publication dateJan 6, 2015
Grant dateJan 6, 2015

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  2. Abstract

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Abstract

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This disclosure provides for adjustment of memory IO timing using a voltage controlled oscillator (VCO) and a register that generates a VCO control voltage directly used to vary memory IO timing. The register may be externally programmable by a controller and may be located on a memory device (IC, module or other device) or on an external voltage generator, which then provides an adjustable voltage to the memory device. This structure may be used to adjust memory timing so as to achieve a minimum target bitrate and thus minimize frequency of operation to minimize power. In one embodiment, each of several memory devices may be independently adjusted in this way to achieve a mesochronous memory system; in another embodiment, memory devices may be have their timing adjusted in parallel, with all memory devices equal to or greater than a target bitrate. Teachings presented herein provide a way to relax overdesign requirements and “tune” fast-fast and slow-slow devices to effectively operate as typical devices.

First claim

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We claim: 1. A memory device, comprising: a memory core; a programmable oscillator that generates a timing signal based on information stored in an externally-programmable register; and a data interface for timing exchange of data with an external data channel based on the timing signal; where the data interface includes a transmitter to time the transmission of read data to a memory controller according to a transmit clock signal, the transmit clock signal generated using t…

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What does patent US8930740B2 cover?
This disclosure provides for adjustment of memory IO timing using a voltage controlled oscillator (VCO) and a register that generates a VCO control voltage directly used to vary memory IO timing. The register may be externally programmable by a controller and may be located on a memory device (IC, module or other device) or on an external voltage generator, which then provides an adjustable vol…
Who is the assignee on this patent?
Zerbe Jared L, Best Scott C, Leibowitz Brian L, and 1 more
What technology area does this patent fall under?
Primary CPC classification G06F1/08. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jan 06 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).