Low-power high-performance clock path architecture
US-2024393824-A1 · Nov 28, 2024 · US
US8930740B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8930740-B2 |
| Application number | US-94775810-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 16, 2010 |
| Priority date | Feb 23, 2010 |
| Publication date | Jan 6, 2015 |
| Grant date | Jan 6, 2015 |
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This disclosure provides for adjustment of memory IO timing using a voltage controlled oscillator (VCO) and a register that generates a VCO control voltage directly used to vary memory IO timing. The register may be externally programmable by a controller and may be located on a memory device (IC, module or other device) or on an external voltage generator, which then provides an adjustable voltage to the memory device. This structure may be used to adjust memory timing so as to achieve a minimum target bitrate and thus minimize frequency of operation to minimize power. In one embodiment, each of several memory devices may be independently adjusted in this way to achieve a mesochronous memory system; in another embodiment, memory devices may be have their timing adjusted in parallel, with all memory devices equal to or greater than a target bitrate. Teachings presented herein provide a way to relax overdesign requirements and “tune” fast-fast and slow-slow devices to effectively operate as typical devices.
Opening claim text (preview).
We claim: 1. A memory device, comprising: a memory core; a programmable oscillator that generates a timing signal based on information stored in an externally-programmable register; and a data interface for timing exchange of data with an external data channel based on the timing signal; where the data interface includes a transmitter to time the transmission of read data to a memory controller according to a transmit clock signal, the transmit clock signal generated using t…
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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