Memory package, semiconductor device, and storage device

Patent metadata

Field	Value
Publication number	US-11736098-B2
Application number	US-202217866517-A
Country	US
Kind code	B2
Filing date	Jul 17, 2022
Priority date	Dec 3, 2021
Publication date	Aug 22, 2023
Grant date	Aug 22, 2023

Abstract

A memory package includes a plurality of memory chips, and an interface chip relaying communications between a controller and the plurality of memory chips and receiving a plurality of signals from the plurality of memory chips. The interface chip includes receivers outputting a data signal and a raw clock signal based on the plurality of signals, a delay circuit outputting a delay clock signal by applying an offset delay corresponding to ½ of one unit interval of the data signal and an additional delay to the raw clock signal, and a sampler sampling the data signal in synchronization with a clock signal. The delay circuit outputs the clock signal generated by removing the offset delay from the delay clock signal when the delay clock signal and the data signal have a phase difference corresponding to one unit interval of the data signal.

First claim

What is claimed is:

1. A memory package comprising:
a plurality of memory chips; and
an interface chip configured to relay communications between a controller and the plurality of memory chips and receive a plurality of signals from the plurality of memory chips,
wherein the interface chip includes:
a first receiver configured to output a data signal based on a first signal of the plurality of signals;
a second receiver configured to output a raw clock signal based on a second signal of the plurality of signals;
a delay circuit configured to output a delay clock signal by applying an offset delay corresponding to ½ of one unit interval of the data signal and an additional delay to the raw clock signal, and output a clock signal generated by removing the offset delay from the delay clock signal when the delay clock signal and the data signal have a phase difference corresponding to one unit interval of the data signal; and
a sampler configured to sample the data signal in synchronization with the clock signal output from the delay circuit.

2. The memory package of claim 1 , wherein the delay circuit includes:
a delay locked loop circuit configured to output a first delay code corresponding to the offset delay;
a counter circuit configured to output a second delay code corresponding to the additional delay; and
a delay cell configured to apply the offset delay and the additional delay to the raw clock signal based on the first delay code and the second delay code, and output the clock signal by applying only the additional delay to the raw clock signal when the delay clock signal and the data signal have the phase difference corresponding to one unit interval of the data signal.

3. The memory package of claim 2 , wherein the delay circuit further includes:
a phase detector configured to detect a phase difference between the data signal and the delay clock signal input to the sampler; and
the counter circuit configured to determine the additional delay based on an output of the phase detector.

4. The memory package of claim 2 , wherein the counter circuit is configured to determine the additional delay based on an output of the sampler while the data signal and the delay clock signal are input to the sampler.

5. The memory package of claim 1 , wherein the additional delay is less than the offset delay.

6. The memory package of claim 1 , wherein the first receiver is configured to output the data signal by delaying an amount of a first default delay from the first signal,
wherein the second receiver is configured to output the raw clock signal by delaying an amount of a second default delay from the second signal, and
wherein a sum of a delay difference between the first default delay and the second default delay and the additional delay corresponds to ½ of one unit interval.

7. The memory package of claim 1 , wherein the raw clock signal is a data strobe signal.

8. The memory package of claim 1 , wherein the data signal is a toggle signal repeatedly transitioning between a high level and a low level for each unit interval.

9. The memory package of claim 8 , wherein the plurality of memory chips are configured to output the plurality of signals as toggle signals during a duty cycle correction (DCC) training period of the memory package.

10. The memory package of claim 9 , wherein the plurality of memory chips are configured to output the plurality of signals during at least a portion of a read training period of the memory package after the DCC training period.

11. A semiconductor device comprising:
a first receiver configured to output a data signal based on a first input signal received from outside the semiconductor device;
a second receiver configured to output a raw clock signal based on a second input signal received from outside the semiconductor device;
a delay locked loop circuit configured to output a first delay code;
a first sampler configured to sample the data signal in synchronization with a clock signal;
a counter circuit configured to output a second delay code generated based on a signal detected in at least one of an input terminal and an output terminal of the first sampler; and
a delay cell configured to output a delay clock signal generated by delaying the raw clock signal by applying delays determined based on the first delay code and the second delay code, and output the clock signal generated by removing a delay according to the first delay code from the delay clock signal when a phase difference between the data signal and the delay clock signal corresponds to one unit interval of the data signal.

12. The semiconductor device of claim 11 , further comprising:
a phase detector configured to detect a phase of each of the data signal and the delay clock signal at each input terminal of the first sampler and transmit the detected phase to the counter circuit.

13. The semiconductor device of claim 11 , wherein the counter circuit connected to the output terminal of the first sampler is configured to determine the second delay code with reference to a first sampler output signal from the first sampler while the first sampler samples the data signal in synchronization with the delay clock signal.

14. The semiconductor device of claim 13 , wherein the first sampler is configured to output the first sampler output signal being a toggle signal repeatedly transitioning between a high level and a low level.

15. The semiconductor device of claim 11 , wherein the delay determined based on the first delay code corresponds to ½ of one unit interval of the data signal.

16. The semiconductor device of claim 11 , wherein the delay determined based on the second delay code is less than ½ of one unit interval of the data signal.

17. The semiconductor device of claim 11 , further comprising:
a third receiver configured to output a complementary raw clock signal having a phase difference of 180° from the raw clock signal based on a third input signal received from outside the semiconductor device; and
a second sampler configured to sample the data signal in synchronization with a complementary clock signal output from the delay cell,
wherein the delay cell further configured to output a complementary delay clock signal generated by delaying the complementary raw clock signal by applying delays determined based on the first delay code and a third delay code generated from the counter circuit, and output a complementary clock signal generated by removing a delay based on the first delay code from the complementary delay clock signal when the data signal and the complementary delay clock signal have the same phase.

18. The semiconductor device of claim 17 , wherein the second delay code is different from the third delay code, and
wherein the delay cell is configured to output the clock signal and the complementary clock signal using a delay based on an average code corresponding to an average of the second delay code and the third delay code.

19. A storage device comprising:
a controller configured to sequentially execute a plurality of training operations;
a memory chip configured to output a first signal and a second signal having the same phase through a first pad and a second pad, respectively, while at least one of the training operations is executed; and
an interface chip connected between the controller and the memory chip, and the interface chip including:
a first receiver configured to output a data signal based on the first signal;
a second receiver configured to output a raw clock signal based

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Tongsung
• Jo Youngmin
• Yoon Chiweon
• Chun Byungkwan
• Jeong Byunghoon

Classifications

• G11C7/222 Primary

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• H03K5/14 Primary

  by the use of delay lines (H03K5/133 takes precedence) · CPC title

• H03K5/135

  by the use of time reference signals, e.g. clock signals · CPC title

• H03L7/0816

  the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input · CPC title

• H03K2005/00247

  using counters · CPC title