Three-dimensional memory device and method of making thereof using selective metal nitride deposition on dielectric metal oxide blocking dielectric

Patent metadata

Field	Value
Publication number	US-12457744-B2
Application number	US-202217932942-A
Country	US
Kind code	B2
Filing date	Sep 16, 2022
Priority date	Sep 16, 2022
Publication date	Oct 28, 2025
Grant date	Oct 28, 2025

Abstract

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a set of dielectric-metal-oxide blocking dielectric portions located at levels of the electrically conductive layers, a memory material layer, and a vertical semiconductor channel. Each of the electrically conductive layers includes a tubular metal nitride portion and a metal fill material portion, each of the tubular metal nitride portions laterally surrounds and contacts a respective one of the dielectric-metal-oxide blocking dielectric portions, and each metal fill material portion either contacts respective overlying and underlying insulating layers of the insulating layers, or contacts respective upper and lower metal nitride liner portions which have a smaller thickness than the tubular metal nitride portions.

First claim

What is claimed is:

1. A three-dimensional memory device, comprising:
an alternating stack of insulating layers and electrically conductive layers;
a memory opening vertically extending through the alternating stack; and
a memory opening fill structure located in the memory opening and comprising a set of dielectric-metal-oxide blocking dielectric portions located at levels of the electrically conductive layers, a memory material layer, and a vertical semiconductor channel,
wherein:
each of the electrically conductive layers comprises a tubular metal nitride portion and a metal fill material portion;
each of the tubular metal nitride portions of the electrically conductive layers laterally surrounds and contacts a respective one of the dielectric-metal-oxide blocking dielectric portions;
each metal fill material portion either contacts respective overlying and underlying insulating layers of the insulating layers, or contacts respective upper and lower metal nitride liner portions which have a smaller thickness than the tubular metal nitride portions; and
the set of dielectric-metal-oxide blocking dielectric portions comprise discrete dielectric-metal-oxide blocking dielectric portions each of which comprises a respective cylindrical outer sidewall that vertically extends from a respective underlying insulating layer of the insulating layers to a respective overlying insulating layer of the insulating layers, an annular top surface in contact with the respective overlying insulating layer, and an annular bottom surface in contact with the respective underlying insulating layer.

2. The three-dimensional memory device of claim 1 , wherein each of the tubular metal nitride portions comprises a respective cylindrical inner sidewall that contacts an entirety of a cylindrical outer sidewall of a respective one of the discrete dielectric-metal-oxide blocking dielectric portions.

3. The three-dimensional memory device of claim 1 , wherein:
the discrete dielectric-metal-oxide blocking dielectric portions are vertically spaced apart from each other; and
each of the discrete dielectric-metal-oxide blocking dielectric portions is in direct contact with and has a same vertical extent as a respective one of the electrically conductive layers within the alternating stack.

4. The three-dimensional memory device of claim 3 , wherein cylindrical inner sidewalls of the discrete dielectric-metal-oxide blocking dielectric portions are vertically coincident with sidewalls of the insulating layers of the alternating stack that are located around the memory opening.

Assignees

• Sandisk Technologies Llc
• Sandisk Technologies Inc

Inventors

• Hinoue Tatsuya
• Uno Tomohiro

Classifications

• H10B63/34

  of the vertical channel field-effect transistor type · CPC title

• H10B51/20

  characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title