Cobalt-containing conductive layers for control gate electrodes in a memory structure

Patent metadata

Field	Value
Publication number	US-9984963-B2
Application number	US-201615223729-A
Country	US
Kind code	B2
Filing date	Jul 29, 2016
Priority date	Feb 4, 2015
Publication date	May 29, 2018
Grant date	May 29, 2018

Abstract

A memory stack structure including a memory film and a vertical semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, a backside blocking dielectric layer is formed in the backside recesses and sidewalls of the memory stack structures. A metallic barrier material portion can be formed in each backside recess. A cobalt metal portion can be formed in each backside recess. Each backside recess can be filled with a portion of a backside blocking dielectric layer, a metallic barrier material portion, a cobalt metal portion, and a metallic material portion including a material other than cobalt.

First claim

What is claimed is:

1. A three-dimensional memory device comprising:
a stack of alternating layers comprising insulator layers and electrically conductive layers and located over a substrate;
a memory opening extending through the stack; and
a memory stack structure comprising at least one charge storage element, a tunneling dielectric, and a vertical semiconductor channel and is located within the memory opening,
wherein each of the electrically conductive layers comprises a cobalt metal portion consisting essentially of cobalt, a metallic material portion containing a material other than cobalt which comprises tungsten, molybdenum or ruthenium, and directly contacting the cobalt metal portion, and a metallic barrier material portion directly contacting the cobalt metal portion and the metallic material portion.

2. The three-dimensional memory device of claim 1 , further comprising a backside blocking dielectric layer comprising horizontal portions located between each vertically neighboring pair of an insulating layer and an electrically conductive layer within the stack of alternating layers.

3. The three-dimensional memory device of claim 2 , wherein the backside blocking dielectric layer further comprises vertical portions adjoining a respective vertically neighboring pair of horizontal portions of the backside blocking dielectric layer and contacting a sidewall of the memory stack structure.

4. The three-dimensional memory device of claim 2 , wherein the metallic barrier material portion contacts a respective pair of horizontal portions of the backside blocking dielectric layer.

5. The three-dimensional memory device of claim 4 , further comprising a backside contact via structure extending through a backside contact trench in the stack, electrically isolated from the electrically conductive layers, and contacting a source region located in the substrate.

6. The three-dimensional memory device of claim 5 , wherein a proximal sidewall of each cobalt metal portion is laterally spaced from a respective vertical portion of the backside blocking dielectric layer by a vertical portion of a respective metallic barrier material portion, and each cobalt metal portion is laterally recessed from the backside contact trench.

7. The three-dimensional memory device of claim 4 , wherein each cobalt metal portion contacts a surface of a respective metallic barrier material portion.

8. The three-dimensional memory device of claim 4 , wherein each cobalt metal portion contacts a pair of horizontal surfaces of the respective metallic barrier material portion and an outer sidewall of the respective metallic barrier material portion.

9. The three-dimensional memory device of claim 2 , wherein the metallic barrier material portion directly contacts the backside blocking dielectric layer.

10. The three-dimensional memory device of claim 9 , wherein the metallic material portion contacts the metallic barrier material portion, and wherein a concave surface of the metallic material portion contacts a convex surface of the cobalt metal portion.

11. The three-dimensional memory device of claim 1 , wherein the metallic material portion comprises a material having a melting point at 1 atmospheric pressure of greater than 2,000 degrees Celsius.

12. The three-dimensional memory device of claim 11 , wherein the metallic material portion comprises a tungsten-containing intermetallic alloy.

13. The three-dimensional memory device of claim 1 , wherein:
the three-dimensional memory device comprises a vertical NAND device located in a device region;
the electrically conductive layers comprise, or are electrically connected to, a respective word line of the vertical NAND device;
the device region comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate;
a plurality of charge storage regions, each charge storage region located adjacent to a respective one of the plurality of semiconductor channels; and
a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate;

the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level;
the electrically conductive layers in the stack are in electrical contact with the plurality of control gate electrodes and extend from the device region to a contact region including a plurality of electrically conductive via connections; and
the substrate comprises a silicon substrate containing a driver circuit for the vertical NAND device.

14. The three-dimensional memory device of claim 1 , wherein the metallic material portion consists essentially of a single elemental metal or an intermetallic alloy of at least two elemental metals.

15. The three-dimensional memory device of claim 14 , wherein the metallic barrier material portion is a portion of a conductive metallic nitride.

16. The three-dimensional memory device of claim 14 , wherein the metallic barrier material portion is a TiN portion, a TaN portion, a WN portion, or a combination thereof.

17. The three-dimensional memory device of claim 14 , wherein:
a concave surface of the metallic material portion directly contacts a convex surface of the cobalt metal portion;
a horizontal surface of the cobalt portion directly contacts the metallic barrier material portion; and
a horizontal surface of the metallic material portion directly contacts the barrier material portion.

Assignees

• Sandisk Technologies Llc

Inventors

• Peri Somesh
• Sharangpani Rahul
• Makala Raghuveer S
• Kanakamedala Senaka
• Shukla Keerti

Classifications

• H10W20/4403

  based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence) · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/43

  Layouts of interconnections · CPC title