Molybdenum-containing conductive layers for control gate electrodes in a memory structure

Patent metadata

Field	Value
Publication number	US-9780182-B2
Application number	US-201514751689-A
Country	US
Kind code	B2
Filing date	Jun 26, 2015
Priority date	Feb 4, 2015
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

A memory film and a semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, a metallic barrier material portion can be formed in each backside recess. A molybdenum-containing portion can be formed in each backside recess. Each backside recess can be filled with a molybdenum-containing portion alone, or can be filled with a combination of a molybdenum-containing portion and a metallic material portion including a material other than molybdenum.

First claim

What is claimed is:

1. A three-dimensional memory device comprising:
a stack of alternating layers comprising insulator layers and electrically conductive layers and located over a substrate;
memory stack structures extending through the stack of alternating layers, wherein each of the memory stack structures includes a memory film and a semiconductor channel located inside the memory film, and the memory film comprises a blocking dielectric, at least one charge storage element, and a tunneling dielectric contacting the semiconductor channel; and
a backside contact trench laterally offset from the memory stack structures and vertically extending through the stack of alternating layers and including a backside contact structure comprising a conductive material therein, wherein the conductive material of the backside contact structure extends through the stack of alternating layers, is electrically isolated from the electrically conductive layers by an insulating spacer that laterally surrounds the backside contact structure and continuously extends from a topmost layer of the stack of alternating layers to a bottommost layer of the stack of alternating layers, and wherein the backside contact structure and the insulating spacer physically contact a semiconductor material portion in the substrate,

wherein:
each of the electrically conductive layers comprises a molybdenum containing portion, a metallic material portion consisting essentially of tungsten or an intermetallic alloy of tungsten and the molybdenum-containing portion, and a metallic barrier material portion;
the metallic barrier material portion embeds a combination of the molybdenum containing portion and the metallic material portion;
the molybdenum containing, portion is spaced from the metallic barrier material portion by the metallic material portion;
the metallic barrier material portion includes a upper horizontal portion and a lower horizontal portion that laterally extend parallel to a top surface of the substrate and a vertical portion adjoined to the upper horizontal portion and the lower horizontal portion of the metallic barrier material portion;
the metallic material portion includes a upper horizontal portion and a lower horizontal portion that laterally extend parallel to the top surface of the substrate and a vertical portion adjoined to the upper horizontal portion and the lower horizontal portion of the metallic material portion, wherein the upper horizontal portion of the metallic material portion contacts a bottom surface of the upper horizontal portion of the metallic barrier material portion, the lower horizontal portion of the metallic material portion contacts a top surface of the lower horizontal portion of the metallic barrier material portion, and a first sidewall of the vertical portion of the metallic material portion contacts a sidewall of the vertical portion of the metallic barrier material portion; and
the molybdenum-containing portion including a top surface that contacts a bottom surface of the upper horizontal portion of the metallic material portion, a bottom surface that contacts a top surface of the lower horizontal portion of the metallic material portion, and a first sidewall that contacts a second sidewall of the vertical portion of the metallic material portion; and
an outer sidewall of the insulating spacer physically contacts a sidewall of each upper horizontal portion of the metallic barrier material portions, a sidewall of each lower horizontal portion of the metallic barrier material portions, a sidewall of each upper horizontal portion of the metallic material portions, a sidewall of each lower horizontal portion of the metallic material portions, and a second sidewall of each of the molybdenum-containing portions.

2. The three-dimensional memory device of claim 1 , wherein the electrically conductive layers comprise:
a first control gate electrode located in a first device level; and
a second control gate electrode located in a second device level that is located below the first device level.

3. The three-dimensional memory device of claim 1 , wherein:
the three-dimensional memory device comprises a vertical NAND device located in a device region; and
the electrically conductive layers comprise, or are electrically connected to a respective word line of the vertical NAND device.

4. The three-dimensional memory device of claim 3 , wherein:
the device region comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate;
a plurality of charge storage regions, each charge storage region located adjacent to a respective one of the plurality of semiconductor channels; and
a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate;

the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level;
the electrically conductive layers in the stack are in electrical contact with the plurality of control gate electrodes and extend from the device region to a contact region including a plurality of electrically conductive via connections; and
the substrate comprises a silicon substrate containing a driver circuit for the NAND device.

5. The three-dimensional memory device of claim 1 , wherein the molybdenum-containing portion is selected from pure molybdenum, a molybdenum tungsten alloy, a molybdenum tungsten and phosphorus alloy, a molybdenum manganese alloy or a molybdenum titanium alloy.

6. The three-dimensional memory device of claim 1 , wherein each of the metallic barrier material portions is a metal nitride barrier material layer having a thickness of 1 to 2 nm which is located between the molybdenum-containing portion and the blocking dielectric.

7. The three-dimensional memory device of claim 1 , wherein the molybdenum-containing portion does not physically contact the metallic barrier material portion.

8. The three-dimensional memory device of claim 1 , wherein each of the metallic barrier material portions is a conductive metallic nitride layer.

9. The three-dimensional memory device of claim 8 , wherein each of the metallic barrier material portions consists essentially of a material selected from TiN, TaN, WN, a combination thereof, and an alloy thereof.

10. The three-dimensional memory device of claim 1 , wherein each of the metallic barrier material portions consists essentially of cobalt, tungsten, copper, ruthenium, or titanium, or a combination thereof.

11. The three-dimensional memory device of claim 1 , wherein each of the molybdenum-containing portions is laterally spaced from the blocking dielectric by the vertical portions of the metallic barrier material portions and the metallic material portions.

12. The three-dimensional memory device of claim 1 , wherein the molybdenum-containing portion consists essentially of molybdenum.

13. The three-dimensional memory device of claim 1 , wherein each of the metallic barrier material portions physically contacts a portion of a sidewall of the blocking dielectric.

14. The three-dimensional memory device of claim 1 , wherein each of the metallic barrier material portions physically contacts an overlying insulator layer in the stack of alternating layers and physically contacts an underlying insulator layer in the stack of alternating layers.

15. The three-dimensional memory device of claim 1 , wherein th

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Peri Somesh
• Makala Raghuveer S
• Koka Sateesh
• Lee Yao-Sheng
• Alsmeier Johann
• Matamis George

Classifications

• H01L27/11548

  Electricity · mapped topic

• H01L27/11556

  Electricity · mapped topic

• H01L29/7926

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic

• H01L27/11573

  Electricity · mapped topic