Etch stop layer for semiconductor devices

Patent metadata

Field	Value
Publication number	US-12451393-B2
Application number	US-202217732695-A
Country	US
Kind code	B2
Filing date	Apr 29, 2022
Priority date	Jun 29, 2016
Publication date	Oct 21, 2025
Grant date	Oct 21, 2025

Abstract

A semiconductor device includes a substrate, a first conductive feature over a portion of the substrate, and an etch stop layer over the substrate and the first conductive feature. The etch stop layer includes a silicon-containing dielectric (SCD) layer and a metal-containing dielectric (MCD) layer over the SCD layer. The semiconductor device further includes a dielectric layer over the etch stop layer, and a second conductive feature in the dielectric layer. The second conductive feature penetrates the etch stop layer and electrically connects to the first conductive feature.

First claim

What is claimed is:

1. A method comprising:
providing a precursor having a substrate, a first dielectric layer over the substrate, and a first conductive feature in the first dielectric layer;
forming a silicon-containing dielectric layer over the first dielectric layer;
forming a metal-containing dielectric layer over the silicon-containing dielectric layer;
forming a second dielectric layer over the metal-containing dielectric layer; and
etching the second dielectric layer to form a first trench, the first trench exposing the metal-containing dielectric layer,
wherein the etching of the second dielectric layer etches the second dielectric layer faster than it etches the metal-containing dielectric layer.

2. The method of claim 1 , further comprising:
etching the metal-containing dielectric layer and the silicon-containing dielectric layer through the first trench to expose the first conductive feature; and
forming a second conductive feature within the first trench directly on the exposed first conductive feature,
wherein the metal-containing dielectric layer and the silicon-containing dielectric layer etches the metal-containing dielectric layer and the silicon-containing dielectric layer faster than it etches the second dielectric layer.

3. The method of claim 1 , further comprising etching the first dielectric layer to for a second trench within the first dielectric layer, and
wherein the forming of the silicon-containing dielectric layer over the first dielectric layer includes forming the silicon-containing dielectric layer in the second trench, and
wherein the forming of the metal-containing dielectric layer over the first dielectric layer includes forming the metal-containing dielectric layer in the second trench.

4. The method of claim 3 , further comprising:
forming a material within the second trench directly on the metal-containing dielectric layer; and
removing the material from the second trench to form an airgap, wherein the metal-containing dielectric layer and the second dielectric layer define boundaries of the airgap.

5. The method of claim 1 , further comprising forming another silicon containing dielectric layer over the metal-containing dielectric layer prior to the forming of the second dielectric layer over the metal-containing dielectric layer.

6. The method of claim 1 , wherein the silicon-containing dielectric layer includes silicon and one of oxygen, carbon and nitrogen, and
wherein the metal-containing dielectric layer includes an oxide of a metal or a nitride of the metal, the metal being selected from the group consisting of aluminum, tantalum, titanium and hafnium.

7. The method of claim 1 , wherein the first conductive feature includes a material selected from the group consisting of copper, aluminum, tungsten and cobalt.

8. A method comprising:
providing a precursor having a substrate, a first dielectric layer over the substrate, and a first conductive feature in the first dielectric layer;
forming a first trench in the first dielectric layer adjacent the first conductive feature;
conformally forming a first etch stop layer having a first composition in the first trench, the first etch stop layer interfacing a top surface of the first conductive feature;
conformally forming a second etch stop layer in the first trench over the first etch stop layer, the second etch stop layer having a second composition that is different from the first composition and being spaced apart from the top surface of the first conductive feature by the first etch stop layer;
forming a decomposable material within the first trench;
forming a second dielectric layer on the decomposable material; and
performing a treatment process to remove the decomposable material thereby forming an air gap extending from the second dielectric layer to the second etch stop layer.

9. The method of claim 8 , further comprising:
forming a second trench extending through the second dielectric layer, the second etch stop layer and the first etch stop layer to expose the first conductive feature; and
forming a second conductive feature on the exposed first conductive feature.

10. The method of claim 9 , wherein the forming of the second trench occurs after the performing of the treatment process.

11. The method of claim 8 , wherein the first composition includes a silicon-containing material and the second composition includes a metal-containing material.

12. The method of claim 8 , wherein the performing of treatment process to remove the decomposable material includes performing a thermal treatment process.

13. The method of claim 8 , wherein the performing of treatment process to remove the decomposable material includes performing an ultra-violet light treatment process.

14. The method of claim 8 , wherein the decomposable material includes neopentyl methacrylate-co-ethylene glycol dimethacrylate copolymer, polypropylene glycol (PPG), polybutadiene (PB), polyethylene glycol (PEG), or polycaprolactone diol (PCL).

15. The method of claim 8 , wherein the forming of the decomposable material within the first trench includes forming the decomposable material directly on the second etch stop layer within the first trench.

16. A method, comprising:
providing a precursor having a first dielectric layer and a first conductive feature in the first dielectric layer;
depositing over the first dielectric layer and the first conductive feature a multilayer etch stop layer (ESL) that includes:
a silicon-containing dielectric layer interfacing the first dielectric layer and the first conductive feature, and
a metal-containing dielectric layer spaced apart from the first dielectric layer and the first conductive feature by the silicon-containing dielectric layer;

depositing a second dielectric layer over the multilayer ESL;
performing a first etch process to etch the second dielectric layer to expose the multilayer ESL in a trench; and
performing a second etch process to extend the trench through the multilayer ESL,
wherein the first etch process etches the second dielectric layer faster than it does the metal-containing dielectric layer,
wherein the second etch process etches the metal-containing dielectric layer and the silicon-containing dielectric layer faster than it does the second dielectric layer.

17. The method of claim 16 , wherein the depositing of the multilayer ESL is performed in a same process chamber.

18. The method of claim 16 ,
wherein the silicon-containing dielectric layer comprises silicon and at least one of oxygen, carbon and nitrogen,
wherein the metal-containing dielectric layer comprises a metal oxide or a metal nitride.

19. The method of claim 18 , wherein the metal-containing dielectric layer comprises aluminum nitride, aluminum oxide, tantalum oxide, titanium oxide, or hafnium oxide.

20. The method of claim 16 ,
wherein the silicon-containing dielectric layer comprises a thickness between 5 Å and 300 Å,
wherein the metal-containing dielectric layer comprises a thickness between 5 Å and 100 Å.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tung Szu-Ping
• Wang Jen-Hung
• Pan Shing-Chyang

Classifications

• H10W20/4403

  based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence) · CPC title

• H10W20/084

  for dual-damascene structures · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title