Semiconductor structure and method making the same

Patent metadata

Field	Value
Publication number	US-9659857-B2
Application number	US-201314106460-A
Country	US
Kind code	B2
Filing date	Dec 13, 2013
Priority date	Dec 13, 2013
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a substrate including a conductive feature; forming aluminum (Al)-containing dielectric layer on the conductive feature; forming a low-k dielectric layer on the Al-containing dielectric layer; and etching the low-k dielectric layer to form a contact trench aligned with the conductive feature. A bottom of the contact trench is on a surface of the Al-containing dielectric layer.

First claim

What is claimed is:

1. A method for forming an integrated circuit (IC) structure, comprising:
providing a substrate including a first conductive feature;
forming a cap layer on the first conductive feature such that a width of the cap layer is substantially similar to a width of the first conductive feature, wherein the cap layer includes at least one metal from the group consisting of: Co, Mn, Ni, Ru, and Ti;
forming an Al-containing dielectric layer on the cap layer, wherein the Al-containing dielectric layer extends beyond the cap layer and the first conductive feature horizontally, and wherein the Al-containing dielectric layer includes: Al with a composition in a range from about 5 wt % to about 20 wt %, O with a composition in a range from about 60 wt % to about 80 wt %, and N with a composition in a range from about 10 wt % to about 30 wt %;
forming a low-k dielectric layer on the Al-containing dielectric layer;
etching the low-k dielectric layer to form a contact trench aligned with the first conductive feature, wherein a bottom of the contact trench is on a surface of the Al-containing dielectric layer; and
forming a second conductive feature in the contact trench, wherein the first conductive feature is coupled to the second conductive feature by the Al-containing dielectric layer.

2. The method of claim 1 , further comprising:
forming an etch stop layer (ESL) between the Al-containing dielectric layer and the low-k dielectric layer; and
etching the ESL to form the contact trench.

3. The method of claim 2 , wherein the forming the ESL includes depositing a layer including at least one of a nitrogen-doped SiC layer or an oxygen-doped SiC layer, wherein the depositing of the layer is performed using a plasma gas, the plasma gas including at least one of CO 2 or N 2 O.

4. The method of claim 2 , wherein the forming the ESL includes depositing a layer including at least one of a nitrogen-doped SiC layer or a Si 3 N 4 layer.

5. The method of claim 2 , wherein the etching the low-k dielectric layer includes a dry etch process using a fluorine-containing etchant, and
wherein the etching the ESL includes a wet etch process which stops at the Al-containing dielectric layer.

6. The method of claim 2 , further comprising:
forming a dielectric layer between the ESL and the low-k dielectric layer; and
etching the dielectric layer to form the contact trench.

7. The method of claim 1 , wherein the forming the Al-containing dielectric layer includes:
performing a NH 3 plasma treatment;
importing an Al-containing organic precursor; and
depositing the Al-containing dielectric layer including Al, N and O.

8. The method of claim 7 , wherein the Al-containing dielectric layer is formed using a process selected from the group consisting of chemical vapor deposition (CVD), atomic layer deposition (ALD), and a combination thereof.

9. The method of claim 8 , wherein the forming the Al-containing dielectric layer includes:
depositing the Al-containing dielectric layer using a chamber pressure in a range from about 0.1 ton to about 100 torr.

10. The method of claim 8 , wherein the forming the Al-containing dielectric layer includes:
depositing the Al-containing dielectric layer using a RF power in a range from about 10 W to about 1000 W.

11. The method of claim 8 , wherein the forming the Al-containing dielectric layer includes:
depositing the Al-containing dielectric layer at a temperature in a range from about 150° C. to about 400° C.

12. The method of claim 8 , wherein the forming the Al-containing dielectric layer includes:
depositing the Al-containing dielectric layer using a flow rate of the NH 3 plasma in a range from about 50 sccm to about 5000 sccm.

13. The method of claim 1 , wherein the Al-containing dielectric layer has a substantially planar bottom surface directly over the first conductive feature that extends beyond the first conductive feature horizontally.

14. A method for forming an integrated circuit (IC) structure, comprising:
providing a substrate including a first conductive feature;
forming a cap layer on the first conductive feature, a width of the cap layer being substantially similar to a width of the first conductive feature;
forming an Al-containing dielectric layer on the cap layer, wherein the Al-containing dielectric layer has a substantially planar bottom surface on the cap layer that extends beyond the cap layer and the first conductive feature horizontally, and wherein the Al-containing dielectric layer is formed with a thickness in a range from about 5 angstroms to about 30 angstroms;
forming an etch stop layer (ESL) on the Al-containing dielectric layer;
forming a low-k dielectric layer on the ESL;
etching the low-k dielectric layer and the ESL to form a contact trench aligned with the first conductive feature, wherein a bottom of the contact trench is on a surface of the Al-containing dielectric layer; and
forming a second conductive feature on the Al-containing dielectric layer directly above the first conductive feature.

15. The method of claim 14 , wherein the etching the low-k dielectric layer and the ESL includes:
dry etching the low-k dielectric layer using a fluorine-containing etchant, and
wet etching the ESL using a hot phosphorous acid (H 3 PO 4 ),
wherein wet etching the ESL stops at the Al-containing dielectric layer.

16. A fabrication method comprising:
receiving a substrate having a first conductive feature disposed thereupon;
forming a capping layer containing a first metal on the first conductive feature;
forming a porous dielectric layer containing a second metal on the capping layer, wherein the second metal is different from the first metal, wherein the porous dielectric layer has a substantially planar bottom surface over the capping layer and the first conductive feature that extends beyond the first conductive feature;
forming an interconnect dielectric layer on the porous dielectric layer; and
forming a second conductive feature within the interconnect dielectric layer, wherein the second conductive feature is coupled to the first conductive feature by the porous dielectric layer.

17. The method of claim 16 , wherein the first metal includes at least one of Co, Mn, Ni, Ru, or Ti, and wherein the second metal includes aluminum.

18. The method of claim 16 further comprising:
forming an etch-stop layer on the porous dielectric layer such that the interconnect dielectric layer is disposed on the etch-stop layer, wherein the etch-stop layer has a different composition than the porous dielectric layer and the interconnect dielectric layer.

19. The method of claim 16 , wherein the first conductive feature includes a barrier layer and a conductive fill material disposed within the barrier layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Huang Hsin-Yen
• Cheng Kai-Fang
• Teng Chi-Lin
• Cheng Hai-Ching
• Bao Tien-I

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P14/69391

  the material containing aluminium, e.g. Al2O3 · CPC title

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

• H10P14/6336

  in the presence of a plasma [PECVD] · CPC title

• H10P14/6334

  using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329) · CPC title