Semiconductor integrated circuit apparatus and method of manufacturing the same
US-9224832-B2 · Dec 29, 2015 · US
Shallow trench isolation integration methods and devices formed thereby
US9123771B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9123771-B2 |
| Application number | US-201313765723-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 13, 2013 |
| Priority date | Feb 13, 2013 |
| Publication date | Sep 1, 2015 |
| Grant date | Sep 1, 2015 |
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Abstract
Official abstract text for this publication.
Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for forming a semiconductor device, comprising: etching a set of trenches in a substrate; forming a first liner layer over the set of trenches; forming a second liner layer over the first liner layer; filling the set of trenches over the second liner layer with a first fill material; polishing and etching back the first fill material to leave a portion of the first fill material remaining; removing the second liner layer disposed above the…
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Classifications
Electricity · mapped topic
- H10W10/0143Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9123771B2 cover?
- Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs …
- Who is the assignee on this patent?
- Globalfoundries Inc
- What technology area does this patent fall under?
- Primary CPC classification H10W10/0143. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Sep 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).