Rapid oxide etch for manufacturing through dielectric via structures

Patent metadata

Field	Value
Publication number	US-10276439-B2
Application number	US-201715611846-A
Country	US
Kind code	B2
Filing date	Jun 2, 2017
Priority date	Jun 2, 2017
Publication date	Apr 30, 2019
Grant date	Apr 30, 2019

Abstract

After bonding a second substrate to a first substrate through a bonded material layer to provide a bonded structure, through dielectric via (TDV) openings of different depths are concurrently formed in the bonded structure by performing a single anisotropic etch using fluorine-deficient species that are obtained by dissociation of fluorocarbon-containing molecules.

First claim

What is claimed is:

1. A method of forming a structure comprising:
forming a bonded structure comprising a first substrate and a second substrate bonded to each other through a boned material layer, wherein the first substrate comprises a stack of a first semiconductor substrate and a first wiring structure comprising at least one first dielectric material layer and at least one first interconnect structure embedded therein, and the second substrate comprises a second semiconductor substrate and a second wiring structure comprising at least one second dielectric material layer and at least one second interconnect structure embedded therein, the first substrate being bonded to the second substrate such that the at least one first dielectric material layer faces and underlies the at least one second dielectric material layer;
concurrently forming a first through dielectric via (TDV) opening and a second TDV opening utilizing a single anisotropic etch and an etching gas containing fluorocarbon-containing molecules having a formula C x F y M, wherein M is chlorine, bromine, sulfur, oxygen or nitrogen, and x is from 2 to 5, and y is from 4 to 10, the first TDV opening extending through the second semiconductor substrate and the at least one second dielectric material layer to expose a last level second conductive line structure in the at least one second interconnect structure, and the second TDV opening extending through the second semiconductor substrate, the at least one second dielectric material layer and the bonded material layer to expose a last level first conductor line structure in the at least one first interconnect structure; and
forming a first TDV structure within the first TDV opening and a second TDV structure within the second TDV opening.

2. The method of claim 1 , wherein the etching gas dissociates during the single anisotropic etch into fluorine-deficient fluorocarbon species.

3. The method of claim 2 , wherein the fluorine-deficient fluorocarbon species comprise CF 2 , CF, CHF 3 , C 4 F 8 , C 5 HF 7 , or C x′ F y′ M, wherein M is chlorine, bromine, sulfur, oxygen, or nitrogen, and wherein x′ is from 1 to 5 and y′ is from 1 to 8.

4. The method of claim 1 , wherein the second TDV opening extends to a greater depth than the first TDV opening.

5. The method of claim 1 , wherein the concurrently forming the first TDV opening and the second TDV opening comprises:
forming a photoresist layer over a backside surface of the second semiconductor substrate;
lithographically patterning the photoresist layer; and
sequentially etching the second semiconductor substrate, the at least one second dielectric material and the bonded material layer by a single anisotropic etch employing remaining portions of the photoresist layer as an etch mask.

6. The method of claim 5 , wherein the second semiconductor substrate, the at least one second dielectric material and the bonded material layer are etched at a rate of 15 nm/s.

7. The method of claim 1 , wherein the first TDV structure extends through the second substrate and contacts the last level second conductive line structure in the at least one second interconnect structure, and the second TDV structure extends through the second substrate and the bonded material layer and contacts the last level first conductive line structure in the at least one first interconnect structure.

8. The method of claim 1 , wherein the forming the first TDV structure in the first TDV opening and the second TDV structure in the second TDV opening comprises:
depositing a conductive material within the first TDV opening and the second TDV opening and on a backside surface of the second semiconductor substrate; and
removing excess portions of the conductive material from the backside surface of the second semiconductor structure.

9. The method of claim 8 , wherein the depositing the conductive material is performed by physical vapor deposition, chemical vapor deposition, electroplating, electroless plating, or combinations thereof.

10. The method of claim 8 , wherein the removing the excess portions of the conductive material is performed by a recess etch, chemical mechanical planarization, or a combination thereof.

11. The method of claim 10 , wherein the forming the first dielectric liner and the second dielectric liner comprises:
forming a dielectric material layer on exposed surfaces of the first TDV opening and the second TDV opening; and
removing horizontal portions of dielectric material layer.

12. The method of claim 1 , further comprising forming a first dielectric liner on sidewalls of the first TDV opening, and a second dielectric liner on sidewalls of the second TDV opening prior to the forming the first TDV structure and the second TDV structure.

13. The method of claim 1 , further comprising forming a third wiring structure over a backside surface of the second semiconductor substrate, wherein the third wiring structure comprising at least one third dielectric material layer and at least one third interconnect structure.

14. The method of claim 13 , wherein the at least one third interconnect structure comprises a third conductive line structure contacting top surfaces of the first TDV structure and the second TDV structure.

15. The method of claim 1 , further forming a first bonding material layer on the first wiring structure.

16. The method of claim 15 , further comprising forming a second bonding material layer on the second wiring structure.

17. The method of claim 15 , wherein the forming the bonded structure comprises:
contacting the second substrate to the first substrate, wherein a surface of the first bonding material layer is in direct contact with a surface of the second bonding material layer; and
introducing an oxide-to-oxide bonding between the first bonding material layer and the second bonding material layer to form a bonded material layer that bonds the first substrate and the second substrate.

18. The method of claim 17 , wherein the oxide-to-oxide bonding is effected by an anneal.

19. The method of claim 18 , wherein the anneal is performed at a temperature ranging from 200° C. to 500° C.

Assignees

• IBM

Inventors

• Engelmann Sebastian U
• Hung Li-Wen
• Joseph Eric
• O'Sullivan Eugene
• Waksman Jeff
• YANG Cornelia Tsang

Classifications

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W20/023 Primary

  the interconnections being through-semiconductor vias · CPC title