Method of making a semiconductor device package

Patent metadata

Field	Value
Publication number	US-2016133546-A1
Application number	US-201614996979-A
Country	US
Kind code	A1
Filing date	Jan 15, 2016
Priority date	Oct 21, 2010
Publication date	May 12, 2016
Grant date	—

Abstract

A semiconductor device package includes a first substrate, which has a lower substrate surface and an upper substrate surface. A conductive dummy gate structure is disposed over the upper substrate surface. An interconnect structure is disposed over the conductive dummy gate structure. The interconnect structure includes a plurality of metal layers disposed within a dielectric structure and at least one of the metal layers is electrically coupled to the conductive dummy gate structure. A conductive through-substrate via extends from the lower substrate surface to an underside of the conductive dummy gate structure and is electrically coupled to the conductive dummy gate structure.

First claim

1 . A semiconductor device package, comprising:
a first substrate including a lower substrate surface and an upper substrate surface; a conductive dummy gate structure disposed over the upper substrate surface; an interconnect structure disposed over the conductive dummy gate structure, wherein the interconnect structure includes a plurality of metal layers disposed within a dielectric structure and wherein at least one of the metal layers is electrically coupled to the conductive dummy gate structure; and a conductive through-substrate via extending from the lower substrate surface to an underside of the conductive dummy gate structure and being electrically coupled to the conductive dummy gate structure.

2 . The semiconductor device package of claim 1 , wherein the conductive through-substrate via makes direct contact with the underside of the conductive dummy gate structure.

3 . The semiconductor device package of claim 1 , wherein the conductive through-substrate via makes electrical connection with a lowermost of the plurality of metal layers through the conductive dummy gate structure and through one or more contact plugs extending between the conductive dummy gate structure and the lowermost of the plurality of metal layers.

4 . The semiconductor device package of claim 3 , wherein the conductive dummy gate structure is made of polysilicon.

5 . The semiconductor device package of claim 1 , wherein the conductive through-substrate via is disposed in a via opening and includes a conformal copper layer whose surface follows contours of the via opening without fully filling the via opening.

6 . The semiconductor device package of claim 5 , wherein the conductive through-substrate via includes a copper-barrier sub-layer and a copper-seed sub-layer.

7 . The semiconductor device package of claim 5 , further comprising:
a polymer layer filling a remainder of the via opening not filled by the conformal copper layer.

8 . The semiconductor device package of claim 7 , further comprising:
a dielectric material covering the lower substrate surface, wherein the via opening extends through the dielectric material and through the first substrate to establish via opening sidewalls; and an isolation layer disposed over a lower surface of the dielectric material and extending along the via opening sidewalls but not covering the underside of the conductive dummy gate structure.

9 . The semiconductor device package of claim 8 , wherein the isolation layer is silicon dioxide, silicon nitride, or a combination of silicon dioxide and silicon nitride.

10 . The semiconductor device package of claim 1 , further comprising:
a second substrate disposed over the interconnect structure, wherein the second substrate includes one or more MEMS devices.

11 . A semiconductor device package, comprising:
a first semiconductor substrate including a lower substrate surface and an upper substrate surface, wherein one or more CMOS devices are disposed on the first substrate; a conductive dummy gate structure disposed over the upper substrate surface; an interconnect structure disposed over the conductive dummy gate structure, wherein the interconnect structure includes a plurality of metal layers disposed within a dielectric structure and wherein at least one of the metal layers is electrically coupled to the conductive dummy gate structure; a second substrate disposed over the interconnect structure, wherein one or more MEMS devices are disposed on the second substrate and are coupled to the one or more CMOS devices through the interconnect structure; and a conductive through-substrate via extending from the lower substrate surface to an underside of the conductive dummy gate structure and being electrically coupled to the conductive dummy gate structure.

12 . The semiconductor device package of claim 11 , further comprising:
a gate dielectric disposed under outer edges of the underside of the conductive dummy gate structure and separating the upper substrate surface from the outer edges of the underside of the conductive dummy gate structure.

13 . The semiconductor device package of claim 12 , wherein the conductive through-substrate via extends past innermost sidewalls of the gate dielectric to make direct contact with the underside of the conductive dummy gate structure.

14 . The semiconductor device package of claim 11 , further comprising spacers disposed about outer edges of the conductive dummy gate structure.

15 . The semiconductor device package of claim 11 , further comprising:
a dielectric layer covering the lower substrate surface, wherein the via opening extends through the dielectric layer and through the first substrate to establish a via opening having via opening sidewalls; an isolation layer covering a lower surface of the dielectric layer and extending along the via opening sidewalls but not covering the underside of the conductive dummy gate structure; a copper-barrier layer covering a lower surface of the isolation layer; and a copper layer covering a lower surface of the copper-barrier layer and being separated from the isolation layer by the copper-barrier layer.

16 . The semiconductor device package of claim 15 , wherein the copper-barrier layer has a thickness ranging from 500 angstroms to 5000 angstroms.

17 . The semiconductor device package of claim 15 , wherein the copper layer has a thickness ranging from 2000 angstroms to 8000 angstroms.

18 . The semiconductor device package of claim 15 , wherein the copper-barrier layer comprises: tantalum, titanium, tantalum nitride, or titanium nitride.

19 . The semiconductor device package of claim 15 :
wherein the copper layer is disposed in the via opening and is a conformal copper layer whose surface follows contours of the via opening without fully filling the via opening, and further comprising: a polymer layer filling a remainder of the via opening not filled by the conformal copper layer.

20 . A semiconductor device package, comprising:
a dielectric layer; a semiconductor substrate including a lower substrate surface and an upper substrate surface, the lower substrate surface in direct contact with the dielectric layer; a conductive dummy gate structure disposed over the upper substrate surface; an interconnect structure disposed over the conductive dummy gate structure, wherein the interconnect structure includes a plurality of metal layers disposed within a dielectric structure and wherein at least one of the metal layers is electrically coupled to the conductive dummy gate structure; a via opening having via opening sidewalls extending from a lower surface of the dielectric layer to an underside of the conductive dummy gate structure; an isolation layer covering the lower surface of the dielectric layer and extending along the via opening sidewalls but not covering the underside of the conductive dummy gate structure; a copper-barrier layer covering a lower surface of the isolation layer; and a copper layer covering a lower surface of the copper-barrier layer and being separated from the isolation layer by the copper-barrier layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yang Hsueh-An

Classifications

• H10W72/942

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title

• H10W72/242

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/90

  Bond pads, in general · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title