Off-center gate cut

Patent metadata

Field	Value
Publication number	US-9607988-B2
Application number	US-201514611090-A
Country	US
Kind code	B2
Filing date	Jan 30, 2015
Priority date	Jan 30, 2015
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

A semiconductor device includes a diffusion area, a gate structure coupled to the diffusion area, and a dummy gate structure coupled to the diffusion area. The gate structure extends a first distance beyond the diffusion area, and the dummy gate structure extends a second distance beyond the diffusion area.

First claim

What is claimed is:

1. A semiconductor device comprising:
a diffusion area;
a second diffusion area;
a gate structure coupled to the diffusion area and to the second diffusion area, the gate structure having a first edge at a first location that is a first distance beyond the diffusion area; and
a dummy gate structure coupled to the diffusion area and to the second diffusion area, the dummy gate structure having a second edge at a second location that is a second distance beyond the diffusion area, wherein the second distance is different than the first distance, and wherein the first edge and the second edge are each between the diffusion area and the second diffusion area.

2. The semiconductor device of claim 1 , wherein the diffusion area, the second diffusion area, the gate structure, and the dummy gate structure are included in a complementary metal oxide semiconductor (CMOS) device.

3. The semiconductor device of claim 1 , wherein the dummy gate structure extends a third distance beyond the second diffusion area.

4. The semiconductor device of claim 1 , wherein the diffusion area is an n-type diffusion area of a complementary metal oxide semiconductor (CMOS) device, and wherein the second diffusion area is a p-type diffusion area of the CMOS device.

5. The semiconductor device of claim 4 , wherein a first driving current of the diffusion area and the second diffusion area is greater than a second driving current of the diffusion area and the second diffusion area if the first distance is greater than the second distance, and wherein the first driving current is less than the second driving current if the first distance is less than the second distance.

6. The semiconductor device of claim 4 , wherein a first driving current of the diffusion area and the second diffusion area is greater than a second driving current of the diffusion area and the second diffusion area if the first distance is less than the third distance, and wherein the first driving current is less than the second driving current if the first distance is greater than the third distance.

7. The semiconductor device of claim 1 , wherein the diffusion area is a p-type diffusion area of a CMOS device, and wherein the second diffusion area is an n-type diffusion area of the CMOS device.

8. The semiconductor device of claim 7 , wherein a first driving current of the diffusion area and the second diffusion area is greater than a second driving current of the diffusion area and the second diffusion area if the first distance is less than the second distance, and wherein the first driving current is less than the second driving current if the first distance is greater than the second distance.

9. The semiconductor device of claim 7 , wherein a first driving current of the diffusion area and the second diffusion area is less than a second driving current of the diffusion area and the second diffusion area if the first distance is less than the third distance, and wherein the first driving current is greater than the second driving current if the first distance is greater than the third distance.

10. The semiconductor device of claim 1 , further comprising a second dummy gate structure coupled to the diffusion area, the second dummy gate structure extending the second distance beyond the diffusion area.

11. The semiconductor device of claim 1 , further comprising a device selected from the group consisting of a mobile phone, a personal digital assistant (PDA), a tablet, a music player, a video player, an entertainment unit, a navigation device, a communications device, a fixed location data unit, and a computer, the semiconductor device comprising at least one semiconductor die that includes the diffusion area, the second diffusion area, the gate structure, and the dummy gate structure.

12. A method of forming a complementary metal oxide semiconductor (CMOS) device, the method comprising:
cutting a gate structure at a first location that is a first distance beyond a diffusion area of the CMOS device, the gate structure coupled to the diffusion area; and
cutting a dummy gate structure at a second location that is a second distance beyond the diffusion area, the dummy gate structure coupled to the diffusion area, wherein the first location and the second location are between the diffusion area and a second diffusion area of the CMOS device, the gate structure coupled to the second diffusion area.

13. The method of claim 12 , further comprising cutting a second dummy gate structure at a third location that is the second distance beyond the diffusion area, the second dummy gate structure coupled to the diffusion area.

14. The method of claim 12 , wherein the dummy gate structure is coupled to the second diffusion area of the CMOS device, and wherein the dummy gate structure extends a third distance beyond the second diffusion area.

15. The method of claim 12 , wherein the diffusion area is an n-type diffusion area of the CMOS device, and wherein the second diffusion area is a p-type diffusion area of the CMOS device.

16. The method of claim 15 , wherein a first driving current of the diffusion area and the second diffusion area is greater than a second driving current of the diffusion area and the second diffusion area if the first distance is greater than the second distance, and wherein the first driving current is less than the second driving current if the first distance is less than the second distance.

17. The method of claim 15 , wherein a first driving current of the diffusion area and the second diffusion area is greater than a second driving current of the diffusion area and the second diffusion area if the first distance is less than the third distance, and wherein the first driving current is less than the second driving current if the first distance is greater than the third distance.

18. The method of claim 12 , wherein the diffusion area is a p-type diffusion area of the CMOS device, and wherein the second diffusion area is an n-type diffusion area of the CMOS device.

19. The method of claim 18 , wherein a first driving current of the diffusion area and the second diffusion area is greater than a second driving current of the diffusion area and the second diffusion area if the first distance is less than the second distance, and wherein the first driving current is less than the second driving current if the first distance is greater than the second distance.

20. The method of claim 18 , wherein a first driving current of the diffusion area and the second diffusion area is less than a second driving current of the diffusion area and the second diffusion area if the first distance is less than the third distance, and wherein the first driving current is greater than the second driving current if the first distance is greater than the third distance.

21. The method of claim 12 , wherein cutting the gate structure and cutting the dummy gate structure is initiated at a processor integrated into an electronic device.

22. A non-transitory computer-readable medium comprising instructions to form a complementary metal oxide semiconductor (CMOS) device, the instructions, when executed by a processor, cause the processor to:
initiate cutting a gate structure at a first location that is a first distance beyond a diffusion area of the CMOS device, the gate structure coupled to the diffusion area; and
initiate cutting a dummy gate structure at a second location that is a second distance beyond the diffusion area, the dummy gate

Assignees

• Qualcomm Inc

Inventors

• Liu Yanxiang
• Song Stanley Seungchul

Classifications

• H10D84/85 Primary

  Complementary IGFETs, e.g. CMOS · CPC title

• H01L21/823871

  Electricity · mapped topic

• H01L27/0207

  Electricity · mapped topic

• H01L21/823828

  Electricity · mapped topic

• H01L27/092 Primary

  Electricity · mapped topic