Magnetic memory device including magnetic tunnel junction patterns with non-uniform widths

Patent metadata

Field	Value
Publication number	US-12439830-B2
Application number	US-202418752866-A
Country	US
Kind code	B2
Filing date	Jun 25, 2024
Priority date	Jan 31, 2020
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

A magnetic memory device includes a lower contact plug on a substrate and a data storage structure on the lower contact plug. The data storage structure includes a bottom electrode, a magnetic tunnel junction pattern, and a top electrode that are sequentially stacked on the lower contact plug. The lower contact plug and the data storage structure have a first thickness and a second thickness, respectively, in a first direction perpendicular to a top surface of the substrate. The first thickness of the lower contact plug is about 2.0 to 3.6 times the second thickness of the data storage structure.

First claim

What is claimed is:

1. A magnetic memory device, comprising:
a bottom electrode, a magnetic tunnel junction pattern, and a top electrode that are sequentially stacked on a substrate,
wherein the magnetic tunnel junction pattern comprises:
a free layer;
a pinned layer between the bottom electrode and the free layer; and
a tunnel barrier layer between the pinned layer and the free layer,

wherein, in a direction parallel to a top surface of the substrate, a middle portion of the pinned layer is wider than an upper portion of the pinned layer and is wider than a lower portion of the pinned layer.

2. The magnetic memory device of claim 1 , wherein, in the direction parallel to the top surface of the substrate, an upper portion of the free layer is wider than a lower portion of the free layer and is wider than the tunnel barrier layer.

3. The magnetic memory device of claim 2 , wherein, in the direction parallel to the top surface of the substrate, the upper portion of the free layer is wider than the upper portion of the pinned layer, is wider than the lower portion of the pinned layer, and is wider than the middle portion of the pinned layer.

4. The magnetic memory device of claim 2 , wherein the free layer has a negative profile at a lateral surface thereof, and wherein the lateral surface of the free layer is inclined at an obtuse angle with respect to a bottom surface of the free layer.

5. The magnetic memory device of claim 4 , wherein the pinned layer comprises a lateral surface that protrudes at the middle portion of the pinned layer beyond the upper portion of the pinned layer and beyond the lower portion of the pinned layer in the direction parallel to the top surface of the substrate.

6. The magnetic memory device of claim 2 , wherein the magnetic tunnel junction pattern further comprises:
a non-magnetic layer between the top electrode and the free layer; and
a capping layer between the top electrode and the non-magnetic layer,
wherein the non-magnetic layer is wider than the lower portion of the free layer and is wider than the tunnel barrier layer.

7. The magnetic memory device of claim 6 , wherein, in the direction parallel to the top surface of the substrate, an upper portion of the capping layer is narrower than a lower portion of the capping layer and is narrower than the non-magnetic layer.

8. The magnetic memory device of claim 7 , wherein, in the direction parallel to the top surface of the substrate, an upper portion of the top electrode is not wider than a lower portion of the top electrode and is not wider than the upper portion of the capping layer.

9. The magnetic memory device of claim 1 , wherein:
the pinned layer is a second pinned layer; and
the magnetic tunnel junction pattern further comprises:
a first pinned layer between the bottom electrode and the second pinned layer; and
a seed layer between the bottom electrode and the first pinned layer,

wherein a lower portion of the first pinned layer is wider than an upper portion of the first pinned layer.

10. The magnetic memory device of claim 9 , wherein, in the direction parallel to the top surface of the substrate, the lower portion of the first pinned layer is wider than the lower portion of the second pinned layer.

11. The magnetic memory device of claim 9 , wherein, in the direction parallel to the top surface of the substrate, an upper portion of the seed layer is wider than the upper portion of the first pinned layer and is narrower than a lower portion of the seed layer.

12. The magnetic memory device of claim 11 , wherein, in the direction parallel to the top surface of the substrate, an upper portion of the bottom electrode is wider than the upper portion of the seed layer and is narrower than a lower portion of the bottom electrode.

13. A magnetic memory device, comprising:
a substrate comprising a cell region and a peripheral circuit region;
a first lower interlayer dielectric layer covering the cell region and the peripheral circuit region;
a plurality of lower lines in the first lower interlayer dielectric layer on the cell region and the peripheral circuit region;
a second lower interlayer dielectric layer on the first lower interlayer dielectric layer and covering the cell region and the peripheral circuit region;
a lower contact plug penetrating the second lower interlayer dielectric layer on the cell region and connected to a corresponding one of the plurality of lower lines;
a data storage structure on the lower contact plug;
a first upper interlayer dielectric layer on the second lower interlayer dielectric layer on the cell region and the peripheral circuit region and covering the data storage structure; and
a peripheral conductive pattern penetrating the first upper interlayer dielectric layer and the second lower interlayer dielectric layer on the peripheral circuit region and connected to corresponding ones of the plurality of lower lines;
wherein the data storage structure comprises a bottom electrode, a magnetic tunnel junction pattern, and a top electrode that are sequentially stacked on the lower contact plug,
wherein the magnetic tunnel junction pattern comprises:
a free layer;
a pinned layer between the bottom electrode and the free layer; and
a tunnel barrier layer between the pinned layer and the free layer,
wherein, in a direction parallel to a top surface of the substrate, a middle portion of the pinned layer is wider than an upper portion of the pinned layer and is wider than a lower portion of the pinned layer, and

wherein the lower contact plug and the data storage structure have a first thickness and a second thickness, respectively, in a first direction perpendicular to a top surface of the substrate,
wherein the first thickness of the lower contact plug is about 2.0 to 3.6 times the second thickness of the data storage structure,
wherein the peripheral conductive pattern includes:
a line pattern that extends in a second direction parallel to the top surface of the substrate; and
a plurality of contact patterns that extend in the first direction from the line pattern and contact the corresponding ones of the plurality of lower lines.

14. The magnetic memory device of claim 13 , wherein:
the line pattern penetrates an upper portion of the first upper interlayer dielectric layer; and
each of the contact patterns penetrates a lower portion of the first upper interlayer dielectric layer and the second lower interlayer dielectric layer, and has a connection with a respective one of the plurality of lower lines.

15. The magnetic memory device of claim 13 , wherein:
a bottom surface of the lower contact plug is in contact with the corresponding one of the plurality of lower lines;
a top surface of the lower contact plug is in contact with the bottom electrode of the data storage structure; and
the first thickness is defined between the bottom surface of the lower contact plug and the top surface of the lower contact plug.

16. The magnetic memory device of claim 13 , further comprising:
an upper line on the data storage structure, wherein the upper line connects the data storage structure to a bit line,
wherein:
a bottom surface of the bottom electrode is in contact with the lower contact plug;
a top surface of the top electrode is in contact with the upper line;
the magnetic tunnel junction pattern is between the bottom electrode and the top electrode; and
the second thickness is defined between the bottom surface of the bottom electrode and the top surface of the top electrode.

17. The magnetic memory devic

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Yongjae
• Chung Kuhoon
• Koh Gwanhyeob
• Kwon Bae-Seong
• Nam Kyungtae

Classifications

• H10N50/01

  Manufacture or treatment · CPC title

• H10B61/20

  comprising components having three or more electrodes, e.g. transistors · CPC title

• H10N50/10

  Magnetoresistive devices · CPC title

• H10B61/22

  of the field-effect transistor [FET] type · CPC title

• H10N50/80 Primary

  Constructional details · CPC title