Integrated magnetic random access memory with logic device

Patent metadata

Field	Value
Publication number	US-10199572-B2
Application number	US-201615164914-A
Country	US
Kind code	B2
Filing date	May 26, 2016
Priority date	May 27, 2015
Publication date	Feb 5, 2019
Grant date	Feb 5, 2019

Abstract

Device and methods of forming a device are disclosed. The method includes providing a substrate defined with at least first and second regions. A first dielectric layer is provided over the first and second regions of the substrate. The first dielectric layer corresponds to pre-metal dielectric (PMD) or CA level which comprises a plurality of contact plugs in the first and second regions. A first interlevel dielectric (ILD) layer is provided over the first dielectric layer. The first ILD layer accommodates a plurality of metal lines in M1 metal level in the first and second regions and via contact in V0 via level in the first region. A magnetic random access memory (MRAM) cell is formed in the second region. The MRAM cell includes a magnetic tunnel junction (MTJ) element sandwiched between the M1 metal level and CA level.

First claim

What is claimed is:

1. A device comprising:
a substrate defined with at least first and second regions, wherein the first region comprises a logic region and the second region comprises a memory region;
a first dielectric layer over the substrate, the first dielectric layer serves as a lower via level;
first and second lower via plugs in first and second lower vias in the first dielectric layer;
a second bottom electrode disposed on top of the second lower via plug in the second region, wherein the second bottom electrode is disposed in the second lower via and is coplanar with a top surface of the first dielectric layer;
a magnetic random access memory (MRAM) element comprising MTJ layers in the second region, wherein the MRAM element contacts the second bottom electrode; and
a second dielectric layer disposed on the first dielectric layer, covering the MRAM element, wherein the second dielectric layer comprises an upper via level and a metal level, the second dielectric layer includes a via contact in the upper via level and a metal line in the metal level in the first region and an upper MRAM element contact in the upper via level and the metal level in the second region, the upper MRAM element contact is electrically coupled to the MRAM element.

2. The device of claim 1 wherein
the lower via level and the upper via level serve as the first contact level which is a lowest via level of the device; and
the metal level serves as the first metal level (M1) which is a lowest metal level of the device.

3. The device of claim 1 comprises
an alignment trench in the first dielectric layer in a third region of the substrate; and
wherein,
the MTJ layers lines sidewalls of the alignment trench, and
the second dielectric layer fills the alignment trench.

4. The device of claim 3 wherein the third region is disposed in a scribe region of the substrate.

5. The device of claim 3 wherein a bottom of the alignment trench between the MTJ layers lining sidewalls of the alignment trench is exposed.

6. The device of claim 5 wherein the third region is disposed in a scribe region of the substrate.

7. The device of claim 1 wherein the second bottom electrode comprises a bottom electrode of the MRAM element.

8. The device of claim 1 comprises a first bottom electrode on top of the first lower via plug, wherein the first bottom electrode is disposed in the first lower via and is coplanar with a top surface of the first dielectric layer.

9. The device of claim 8 wherein the first and second bottom electrode comprises a same material, and wherein the second bottom electrode serves as a bottom electrode of the MRAM element.

10. A device comprising:
at least first, second and third regions, wherein the first region comprises a logic region and the second region comprises a memory region;
a first dielectric layer disposed over the first, second and third regions, the first dielectric layer serves as a lower via level, the first dielectric layer includes first and second lower via plugs in first and second lower vias in the first and second regions and an alignment marker trench in the third region;
a magnetic random access memory (MRAM) element comprising MTJ layers in the second region of the device, wherein the MRAM element contacts the second lower via plug in the second region and the MTJ layers lining sidewalls of the alignment marker trench, wherein the alignment marker trench comprises sidewalls lined with the MTJ layers while a bottom of the alignment marker trench between the MTJ layers is exposed;
a second dielectric layer disposed over the first dielectric layer, the second dielectric layer covers the MRAM element and fills the alignment marker trench lined with the MTJ layers, wherein the second dielectric layer includes an upper via level and a metal level; and
a via contact and a metal line disposed in the first region of the second dielectric layer and an upper MRAM element contact is disposed in the second region of the second dielectric layer.

11. The device of claim 10 wherein the third region is disposed in a scribe region.

12. The device of claim 10 wherein the second lower via plug comprises a second bottom electrode disposed on top of the second lower via plug, the second bottom electrode is disposed within the second lower via and a top surface of the second bottom electrode is coplanar with a top surface of the first dielectric layer.

13. The device of claim 12 wherein the second bottom electrode serves as a bottom electrode of the MRAM element.

14. The device of claim 12 comprises a first bottom electrode disposed on top of the first lower via plug, the first bottom electrode is disposed within the first lower via and a top surface of the first bottom electrode is coplanar with a top surface of the first dielectric layer.

15. A device comprising:
a substrate defined with at least first and second regions, wherein the first region comprises a logic region and the second region comprises a memory region;
a first dielectric layer over the substrate, the first dielectric layer serves as a lower via level of a first contact level of the device;
first and second lower via plugs in first and second lower vias in the first dielectric layer;
a magnetic random access memory (MRAM) element comprising MTJ layers in the second region, wherein the MRAM element contacts the second lower via plug in the second region, wherein the second lower via plug comprises a second bottom electrode disposed on top of the second lower via plug, the second bottom electrode is disposed within the second lower via and a top surface of the second bottom electrode is coplanar with a top surface of the first dielectric layer; and
a second dielectric layer disposed on the first dielectric layer, covering the MRAM element, wherein the second dielectric layer comprises an upper via level and a metal level, the second dielectric layer includes a via contact in the upper via level and a metal line in the metal level in the first region and an upper MRAM element contact in the upper via level and the metal level in the second region, the upper MRAM element contact is electrically coupled to the MRAM element, the upper via level serves as the upper via level of the first contact level of the device and the metal level serves as a first metal level of the device which is a lowest metal level of the device.

16. The device of claim 15 wherein the second bottom electrode serves as a bottom electrode of the MRAM element.

17. The device of claim 15 comprises:
an alignment trench in the first dielectric layer in a third region of the substrate; and
wherein,
the MTJ layers lines sidewalls of the alignment trench, and
the second dielectric layer fills the alignment trench.

18. The device of claim 17 wherein a bottom of the alignment trench between the MTJ layers lining sidewalls of the alignment trench is exposed.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Yi Wanbing
• Jiang Yi
• Wang Daxiang
• Shao Wei
• Tan Juan Boon

Classifications

• H01L43/12 Primary

  Electricity · mapped topic

• H01L27/228

  Electricity · mapped topic

• H10N50/01 Primary

  Manufacture or treatment · CPC title

• H10B61/22 Primary

  of the field-effect transistor [FET] type · CPC title