Integrated magnetic random access memory with logic device

Patent metadata

Field	Value
Publication number	US-10121964-B2
Application number	US-201514862180-A
Country	US
Kind code	B2
Filing date	Sep 23, 2015
Priority date	Sep 23, 2015
Publication date	Nov 6, 2018
Grant date	Nov 6, 2018

Abstract

Integrating magnetic random access memory with logic is disclosed. The magnetic tunnel junction stack of a magnetic memory cell is disposed within a dielectric layer which serves as a via level of an interlevel dielectric layer with a metal level above the via level. An integration scheme for forming dual damascene structures for interconnects can be formed to logic and memory cells easily.

First claim

What is claimed is:

1. A method of forming a device comprising:
providing a substrate defined with at least first and second regions, the first region comprises a memory region for magnetic random access memories (MRAMs) and the second region comprises a logic region, wherein the substrate is prepared with
front-end-of-line (FEOL) components on the substrate in the first and second regions, and
a lower back-end-of-line (BEOL) dielectric layer disposed over the substrate covering the FEOL components, the lower BEOL dielectric layer comprises
L interconnect dielectric (ILD) level, where L is a whole number greater than or equal to 1 but less than x, where x is the total number of ILD levels for the device, and
wherein an i th ILD level of the device comprises a via level V i−1 dielectric below a metal level M i dielectric, where i is from 1 to x, and the via level V i−1 dielectric includes contacts and the metal level M i dielectric includes metal lines;

forming a lower dielectric liner on a metal level M L dielectric, which is a top of the lower BEOL dielectric layer in the first and second regions;
forming a magnetic tunnel junction (MTJ) stack of a magnetic random access memory (MRAM) cell in the first region of the substrate on the lower dielectric liner, the MTJ stack includes a MTJ disposed between top and bottom electrodes, wherein the MTJ stack includes a lower MTJ portion which includes the bottom electrode and an upper MTJ portion which includes the top electrode, the bottom electrode is electrically coupled to a lower metal line in the metal level M L dielectric below through an opening in the lower dielectric liner, wherein the upper MTJ portion and the lower MTJ portion are formed in separate patterning processes, wherein the MTJ stack includes a dielectric liner disposed on the MTJ stack;
forming a dielectric layer on the substrate in the first and second regions, the dielectric layer is disposed on the MTJ stack including the dielectric liner and on the lower dielectric liner, the dielectric layer serves as a via level V i dielectric above the metal level M L dielectric;
forming an upper dielectric liner on the dielectric layer in the first and second regions, wherein the upper dielectric liner is patterned to form first and second openings corresponding to first and second vias of first and second dual damascene structures in the first and second regions;
forming a metal level dielectric layer on the upper dielectric liner with the first and second openings in the first and second regions, wherein the metal level dielectric layer serves as a metal level M i+1 dielectric;
performing a first etch, wherein the first etch
patterns the metal level dielectric layer, which serves as the metal level M i+1 dielectric, to form first and second trenches, and
patterns the dielectric layer, which serves as the via level V i dielectric, using the upper dielectric liner as an etch mask to form the first and second vias, wherein the first via stops at the dielectric liner and the second via stops at the lower dielectric liner; and

performing a second etch, wherein the second etch
patterns the dielectric liner at the first via to expose the top electrode of the MTJ stack, and the lower dielectric liner at the second via to expose a logic metal line in the metal level M L dielectric.

2. The method of claim 1 wherein:
the first and second dual damascene structures are filled with metal to form first and second metal lines with first and second via contacts in the first and second dual damascene structures; and
the first metal line of the first dual damascene structure serves as a top metal line.

3. The method of claim 1 wherein forming the MTJ stack comprises:
forming various layers of the MTJ stack on the lower dielectric liner in the first and second regions;
patterning layers of the upper MTJ portion to form the upper MTJ portion in the first region using a first patterning process;
forming the dielectric liner on the substrate, the dielectric liner lines the upper MTJ portion and a top layer of the lower MTJ portion; and
patterning layers of the lower MTJ portion to form the MTJ stack in the first region using a second patterning process with the dielectric liner lining the MTJ stack.

4. The method of claim 3 wherein the second patterning process forms the lower MTJ portion which is larger than the upper MTJ portion.

5. The method of claim 4 wherein:
the layers of the lower MTJ portion comprises
the bottom electrode,
a first fixed layer, and
a first tunneling barrier layer; and

the layers of the upper MTJ portion comprises
a free layer, and
the top electrode.

6. The method of claim 5 wherein the layers of the upper portion comprise a second tunneling barrier layer between the free layer and the top electrode.

7. The method of claim 6 wherein the dielectric layer has a planar top surface.

8. The method of claim 7 comprising planarizing the dielectric layer by chemical mechanical polishing to form the planar top surface.

9. The method of claim 1 wherein the lower dielectric liner comprises:
a first lower dielectric liner on the top of the lower BEOL dielectric layer; and
a second lower dielectric liner on the first lower dielectric liner.

10. The method of claim 9 wherein the first lower dielectric liner on the top of the lower BEOL dielectric layer comprises a low k dielectric layer and serves as an etch stop layer.

11. A method of forming a device comprising:
providing a substrate defined with at least first and second regions, the first region comprises a memory region for magnetic random access memories (MRAMs) and the second region comprises a logic region, wherein the substrate is prepared with
front-end-of-line (FEOL) components on the substrate in the first and second regions, and
a lower back-end-of-line (BEOL) dielectric layer disposed over the substrate covering the FEOL components, the lower BEOL dielectric layer comprises
L interconnect dielectric (ILD) level, where L is a whole number greater than or equal to 1 but less than x, where x is the total number of ILD levels for the device, and
wherein an i th ILD level of the device comprises a via level V i−1 dielectric below a metal level M i dielectric, where i is from 1 to x, and the via level V i−1 dielectric includes contacts and the metal level M i dielectric includes metal lines;

forming a lower dielectric liner on a metal level M L dielectric, which is a top of the lower BEOL dielectric layer in the first and second regions, wherein the lower dielectric liner comprises
a first lower dielectric liner on the top of the lower BEOL dielectric layer, and
a second lower dielectric liner on the first lower dielectric liner;

forming a magnetic tunnel junction (MTJ) stack of a magnetic random access memory (MRAM) cell in the first region of the substrate on the lower dielectric liner, the MTJ stack includes a MTJ disposed between top and bottom electrodes, wherein the MTJ stack includes a lower MTJ portion which includes the bottom electrode and an upper MTJ portion which includes the top electrode, the bottom electrode is electrically coupled to a lower metal line in the metal level M L dielectric below through an opening in the lower dielectric liner, wherein the upper MTJ portion and the lower MTJ portion are formed in separate patterning processes, wherein the MTJ stack includes a dielectric liner disposed on the MTJ stack;
forming a dielectric layer on the substrate in the first and second regions, the dielectric layer is disposed on the MTJ stack including the dielectric liner and on the lower dielectric liner, the dielectric layer serves as a via

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Tan Juan Boon
• Jiang Yi
• Wang Daxiang
• Zhang Fan
• Poh Francis
• Shum Danny Pak-Chum

Classifications

• H01L27/228

  Electricity · mapped topic

• H01L43/08

  Electricity · mapped topic

• H01L43/12 Primary

  Electricity · mapped topic

• H10N50/10

  Magnetoresistive devices · CPC title

• H10B61/22 Primary

  of the field-effect transistor [FET] type · CPC title