Semiconductor memory structure with magnetic tunnel junction (MTJ) cell

Patent metadata

Field	Value
Publication number	US-10276634-B2
Application number	US-201715627646-A
Country	US
Kind code	B2
Filing date	Jun 20, 2017
Priority date	Jun 20, 2017
Publication date	Apr 30, 2019
Grant date	Apr 30, 2019

Abstract

A semiconductor memory structure is provided. The semiconductor memory structure includes a bottom electrode formed over a substrate and a magnetic tunneling junction (MTJ) cell formed over the bottom electrode. The semiconductor memory structure includes a top electrode formed over the MTJ cell and a passivation layer surrounding the top electrode. The passivation layer has a recessed portion that is lower than a top surface of the top electrode. The semiconductor memory structure further includes a cap layer formed on the top electrode and the passivation layer, wherein the cap layer is formed in the recessed portion.

First claim

What is claimed is:

1. A semiconductor memory structure, comprising:
a bottom electrode formed over a substrate;
a magnetic tunneling junction (MTJ) cell formed over the bottom electrode;
a top electrode formed over the MTJ cell;
a passivation layer formed over the substrate, the passivation layer extending along corresponding sides of the top electrode, wherein a top surface of the passivation layer has a recessed portion that is lower than a top surface of the top electrode;
a dielectric layer formed on the passivation layer, wherein the top surface of the top electrode is level with a top surface of the dielectric layer; and
a conductive cap layer formed on the top electrode, the passivation layer, and the dielectric layer, wherein the conductive cap layer extends along a top surface of the dielectric layer, into the recessed portion, and along the top surface of the top electrode.

2. The semiconductor memory structure as claimed in claim 1 , wherein the MTJ cell comprises:
a first ferromagnetic layer formed on the bottom electrode;
an insulator layer formed on the first ferromagnetic layer; and
a second ferromagnetic layer formed on the insulator layer.

3. The semiconductor memory structure as claimed in claim 2 , wherein the first ferromagnetic layer has a bottom surface with a bottom width, the second ferromagnetic layer has a top surface with a top width, and the bottom width is greater than the top width.

4. The semiconductor memory structure as claimed in claim 1 , wherein the recessed portion has a depth, and the top electrode has a height, and a ratio of the depth to the height is in a range from about 40% to about 60%.

5. The semiconductor memory structure as claimed in claim 1 , further comprising:
a transistor device formed over the substrate; and
an interconnect structure formed over the transistor device, wherein the interconnect structure comprises a metal layer, and the metal layer is electrically connected to the bottom electrode.

6. The semiconductor memory structure as claimed in claim 1 , further comprising:
a contact structure formed over the top electrode, wherein the contact structure is electrically connected to the top electrode by the conductive cap layer.

7. The semiconductor memory structure as claimed in claim 6 , wherein the contact structure has a protruding portion extending into a position which is directly above the recessed portion of the passivation layer.

8. The semiconductor memory structure as claimed in claim 1 , further comprising:
a sidewall spacer layer formed on sidewall surfaces of the top electrode and the MTJ cell, wherein a portion of the sidewall spacer layer is between the top electrode and the conductive cap layer.

9. The semiconductor memory structure as claimed in claim 1 , wherein the top electrode has a top surface and a sidewall surface, and the conductive cap layer is in direct contact with the top surface and a portion of the sidewall surface.

10. A semiconductor memory structure, comprising:
a bottom electrode formed over a substrate;
a magnetic tunneling junction (MTJ) cell formed over the bottom electrode;
a top electrode formed over the MTJ cell;
a passivation layer formed over the substrate, the passivation layer extending along corresponding sides of the top electrode and the MTJ cell, wherein a top surface of the passivation layer has a recessed portion, which is lower than a top surface of the top electrode;
a cap layer formed on the top electrode, wherein the cap layer has a protruding portion, which extends into the recessed portion of the passivation layer, and a bottom surface of the protruding portion is lower than the top surface of the top electrode; and
a contact structure formed on the cap layer, wherein the contact structure is separated from the top electrode by the cap layer.

11. The semiconductor memory structure as claimed in claim 10 , further comprising:
a transistor device formed over the substrate; and
an interconnect structure formed over the transistor device, wherein the interconnect structure comprises a metal layer, and the metal layer is electrically connected to the bottom electrode.

12. The semiconductor memory structure as claimed in claim 11 , further comprising:
a drain region formed in the substrate; and
a source region formed in the substrate, wherein the drain region and the source region are at opposite sides of the transistor device, and the drain region is electrically connected to the bottom electrode.

13. The semiconductor memory structure as claimed in claim 10 , wherein the MTJ cell comprises:
a first ferromagnetic layer formed on the bottom electrode;
an insulator layer formed on the first ferromagnetic layer; and
a second ferromagnetic layer formed on the insulator layer.

14. The semiconductor memory structure as claimed in claim 10 , wherein a portion of the cap layer is between the top electrode and the passivation layer.

15. The semiconductor memory structure as claimed in claim 10 ,
wherein a portion of the contact structure is lower than a top surface of the cap layer.

16. A semiconductor memory structure, comprising:
a bottom electrode formed over a substrate;
a first ferromagnetic layer formed on the bottom electrode;
an insulator layer formed on the first ferromagnetic layer;
a second ferromagnetic layer formed on the insulator layer;
a top electrode formed over the second ferromagnetic layer, wherein the top electrode comprises a top surface and a sidewall surface;
a passivation layer surrounding the sidewall surface of the top electrode, wherein a top surface of the passivation layer adjacent the top electrode has a recessed portion, which is lower than a top surface of the top electrode; and
a cap layer formed on the top electrode, wherein the cap layer extends into the recessed portion of the passivation layer, the top surface and a portion of the sidewall surface of the top electrode are in direct contact with the cap layer, and the cap layer is electrically connected to the top electrode.

17. The semiconductor memory structure as claimed in claim 16 , further comprising:
a transistor device formed over the substrate;
a drain region formed in the substrate; and
a source region formed in the substrate, wherein the drain region and the source region are at opposite sides of the transistor device, and the bottom electrode is directly over the drain region.

18. The semiconductor memory structure as claimed in claim 16 , further comprising:
a contact structure formed on the cap layer, wherein the contact structure is electrically connected to the top electrode by the cap layer.

19. The semiconductor memory structure as claimed in claim 16 , wherein a bottom surface of the cap layer is higher than a top surface of the first ferromagnetic layer.

20. The semiconductor memory structure as claimed in claim 6 , wherein a projection of the contact structure on a top surface the substrate is in a range of a projection of the conductive cap layer on the top surface of the substrate.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Shih-Wei
• Tseng Yuan-Tai
• Liu Shih-Chang

Classifications

• H01L43/12

  Electricity · mapped topic

• H01L43/02

  Electricity · mapped topic

• H01L43/08

  Electricity · mapped topic

• H01L27/228 Primary

  Electricity · mapped topic

• H10B61/22 Primary

  of the field-effect transistor [FET] type · CPC title