Magnetoresistive random access memory device having magnetic tunnel junction and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10056543-B2
Application number	US-201615146355-A
Country	US
Kind code	B2
Filing date	May 4, 2016
Priority date	Aug 19, 2015
Publication date	Aug 21, 2018
Grant date	Aug 21, 2018

Abstract

In a method of manufacturing an MRAM device, a memory unit including a lower electrode, an MTJ structure and an upper electrode sequentially stacked is formed on a substrate. A protective layer structure including a capping layer, a sacrificial layer and an etch stop layer sequentially stacked is formed on the substrate to cover the memory unit. An insulating interlayer is formed on the protective layer structure. The insulating interlayer is formed to form an opening exposing the protective layer structure. The exposed protective layer structure is partially removed to expose the upper electrode. A wiring is formed on the exposed upper electrode to fill the opening.

First claim

What is claimed is:

1. A method of manufacturing a magnetoresistive random access memory (MRAM) device, comprising:
forming a memory unit on a substrate, the memory unit including a lower electrode, a magnetic tunnel junction (MTJ) structure and an upper electrode that are sequentially stacked;
forming a protective layer structure on the substrate to cover the memory unit, the protective layer structure including a capping layer, a sacrificial layer and an etch stop layer that are sequentially stacked;
partially removing the etch stop layer to expose a portion of the sacrificial layer;
forming an insulating interlayer on the protective layer structure, wherein forming the insulating interlayer on the protective layer structure includes forming the insulating interlayer on the exposed portion of the sacrificial layer;
partially removing the insulating interlayer to form an opening exposing the protective layer structure, wherein the opening is formed to expose the exposed portion of the sacrificial layer;
at least partially removing the exposed protective layer structure to expose the upper electrode; and
forming a wiring in the opening on the exposed upper electrode.

2. The method of claim 1 , wherein partially removing the etch stop layer to expose the portion of the sacrificial layer includes performing an anisotropic etching process on the etch stop layer, so that portions of the etch stop layer except for a portion of the etch stop layer on a sidewall of the memory unit are removed to expose the portion of the sacrificial layer, the exposed portion of the sacrificial layer being on a top surface of the memory unit.

3. The method of claim 1 , wherein at least partially removing the exposed protective layer structure to expose the upper electrode includes:
removing the exposed portion of the sacrificial layer to expose a portion of the capping layer; and
removing the exposed portion of the capping layer to expose the upper electrode.

4. The method of claim 3 , wherein the sacrificial layer includes a material having etching selectivity with respect to both the capping layer and the etch stop layer,
and wherein when the exposed portion of the sacrificial layer is removed to expose the portion of the capping layer, the etch stop layer and the capping layer are not removed.

5. The method of claim 3 , wherein partially removing the insulating interlayer to form the opening exposing the protective layer structure is performed by a dry etching process,
wherein removing the exposed portion of the sacrificial layer to expose the portion of the capping layer is performed by a wet etching process,
and wherein removing the exposed portion of the capping layer to expose the upper electrode is performed by a wet etching process.

6. The method of claim 3 , wherein removing the exposed portion of the sacrificial layer to expose the portion of the capping layer includes removing a portion of the sacrificial layer on a sidewall of the memory unit to expose a portion of the capping layer on the sidewall of the memory unit.

7. The method of claim 1 , wherein partially removing the insulating interlayer to form the opening exposing the protective layer structure includes forming the opening to expose the exposed portion of the sacrificial layer and at least a portion of the etch stop layer on a sidewall of the memory unit.

8. The method of claim 1 , wherein partially removing the insulating interlayer to form the opening exposing the protective layer structure includes forming the opening to expose a portion of the etch stop layer on a top surface of the memory unit.

9. The method of claim 1 , wherein the capping layer has a thickness less than that of the etch stop layer.

10. The method of claim 1 , wherein the capping layer and the etch stop layer have substantially the same material.

11. The method of claim 10 , wherein the capping layer and the etch stop layer include silicon nitride.

12. A method of manufacturing a magnetoresistive random access memory (MRAM) device, comprising:
forming a first structure on a substrate, the first structure including a magnetic tunnel junction (MTJ) structure and an upper electrode on top of the MTJ structure;
forming a layer structure on the substrate to cover the first structure, the layer structure including first, second and third layers sequentially stacked;
partially removing the third layer of the layer structure to form a third layer pattern exposing a portion of the second layer;
forming an insulating interlayer on the layer structure;
partially removing the insulating interlayer to form an opening exposing at least the exposed portion of the second layer;
removing the exposed portion of the second layer to expose a portion of the first layer;
at least partially removing the exposed portion of the first layer to expose the upper electrode; and
forming a bit line on the exposed upper electrode.

13. The method of claim 12 , wherein an etching selectivity of the second layer with respect to the first layer is greater than an etching selectivity of the second layer with respect to the insulating interlayer.

14. The method of claim 13 , wherein the first and third layers include silicon nitride, and the second layer and the insulating interlayer include silicon oxide.

15. The method of claim 12 , wherein an etching selectivity of the second layer with respect to the third layer is greater than an etching selectivity of the second layer with respect to the insulating interlayer.

16. The method of claim 15 , wherein partially removing the insulating interlayer to form the opening exposing at least the exposed portion of the second layer includes forming the opening to expose a sidewall of the third layer pattern.

17. A method of manufacturing a magnetoresistive random access memory (MRAM) device, comprising:
forming a first insulating interlayer on a substrate;
forming a contact plug that penetrates the first insulating interlayer;
forming a memory unit on the contact plug, the memory unit comprising a lower electrode, a magnetic tunnel junction (MTJ) on top of the lower electrode, and an upper electrode on top of the MTJ;
forming a capping layer on top of the memory unit;
forming a sacrificial layer on top of the capping layer;
forming an etch stop layer on top of the sacrificial layer;
removing a portion of the etch stop layer that is on top of the memory unit to expose a portion of the sacrificial layer;
forming an insulating interlayer on the exposed portion of the sacrificial layer;
partially removing the insulating interlayer to expose the exposed portion of the sacrificial layer;
removing the exposed portion of the sacrificial layer that is on top of the memory unit;
removing a portion of the capping layer that is on top of the memory unit; and
forming a wiring structure on the upper electrode.

18. The method of claim 17 , wherein a top surface of the etch stop layer extends higher above the substrate than does a top surface of the capping layer and a top surface of the sacrificial layer.

19. The method of claim 17 , further comprising removing a portion of the sacrificial layer that extends along a first sidewall of the memory unit to form an air gap between a portion of the capping layer that extends along the first sidewall of the memory unit and a portion of the etch stop layer that extends along the first sidewall of the memory unit.

Assignees

• Bak Jung Hoon
• Son Myoung Su
• Shim Jae Chul
• Koh Gwan Hyeob
• Song Yoon Jong
• Samsung Electronics Co Ltd

Inventors

• Bak Jung-Hoon
• Son Myoung-Su
• Shim Jae-Chul
• Koh Gwan-Hyeob
• Song Yoon-Jong

Classifications

• H01L43/08

  Electricity · mapped topic

• H01L43/02 Primary

  Electricity · mapped topic

• H01L43/12

  Electricity · mapped topic

• H01L43/10

  Electricity · mapped topic

• H10N50/01

  Manufacture or treatment · CPC title