Semiconductor device having an air gap surrounding a portion of a conductive contact layer

Patent metadata

Field	Value
Publication number	US-12439587-B2
Application number	US-202217953054-A
Country	US
Kind code	B2
Filing date	Sep 26, 2022
Priority date	Apr 27, 2022
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

A semiconductor device includes; a substrate including an active region including a first region and a second region, a bitline extending in a first direction on the substrate and electrically connected to the first region of the active region, a spacer structure disposed on a side surface of the bitline, a contact structure disposed on a side surface of the spacer structure and electrically connected to the second region of the active region and a data storage structure disposed on the contact structure and electrically connected to the contact structure. The contact structure includes; a conductive contact layer including a first portion and a second portion disposed on the first portion, a barrier layer surrounding the first portion of the conductive contact layer, and an air gap surrounding the second portion of the conductive contact layer.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate including an active region, the active region including a first region and a second region;
a bitline extending in a first direction on the substrate and electrically connected to the first region of the active region;
a spacer structure disposed on a side surface of the bitline;
a contact structure disposed on a side surface of the spacer structure and electrically connected to the second region of the active region; and
a data storage structure disposed on the contact structure and electrically connected to the contact structure,
wherein the contact structure includes:
a conductive contact layer including a first portion and a second portion disposed on the first portion;
a barrier layer surrounding the first portion of the conductive contact layer; and
an air gap surrounding the second portion of the conductive contact layer.

2. The semiconductor device of claim 1 , wherein the air gap is disposed on the barrier layer between the second portion of the conductive contact layer and the spacer structure.

3. The semiconductor device of claim 1 , further comprising:
an upper conductive pattern disposed on the contact structure and including a first protruding portion extending between the spacer structure and the second portion of the conductive contact layer and contacting an upper region of a first side surface of the second portion of the conductive contact layer, wherein the first side surface of the second portion of the conductive contact layer faces the spacer structure.

4. The semiconductor device of claim 3 , further comprising:
a device separation region defining the active region in the substrate;
a word line structure crossing between the first region and the second region of the active region and extending into the device separation region;
an insulating fence vertically overlapping the word line structure and disposed on a side surface of the contact structure; and
a separation insulating pattern penetrating the upper conductive pattern to contact the contact structure and the insulating fence.

5. The semiconductor device of claim 4 , wherein the air gap is disposed on the barrier layer between the second portion of the conductive contact layer and the insulating fence.

6. The semiconductor device of claim 4 , wherein the upper conductive pattern further comprises:
a second protruding portion extending between the insulating fence and the second portion of the conductive contact layer to contact an upper region of a second side surface of the second portion of the conductive contact layer, wherein the second side surface of the second portion of the conductive contact layer faces the insulating fence.

7. The semiconductor device of claim 4 , wherein an upper surface of the barrier layer is at a level lower than that of a lower end of the separation insulating pattern.

8. The semiconductor device of claim 1 , wherein the spacer structure includes an air gap spacer.

9. The semiconductor device of claim 8 , wherein the spacer structure further includes a first spacer between the air gap spacer and the air gap.

10. The semiconductor device of claim 9 , wherein the spacer structure further includes a second spacer between the air gap spacer and the bitline.

11. The semiconductor device of claim 1 , further comprising:
a conductive pattern between the second region of the active region and the contact structure; and
a metal-semiconductor compound layer between the conductive pattern and the contact structure.

12. A semiconductor device, comprising:
a substrate including an active region;
a first bitline extending in a first direction on the substrate and including a first side surface;
a second bitline extending in the first direction and including a second side surface facing the first side surface of the first bitline;
a first spacer structure covering the first side surface of the first bitline;
a second spacer structure covering the second side surface of the second bitline;
a contact structure disposed between the first spacer structure and the second spacer structure and electrically connected to a portion of the active region; and
a data storage structure disposed on the contact structure and electrically connected to the contact structure,
wherein the contact structure includes:
a conductive contact layer;
a barrier layer surrounding a lower surface and lower regions of side surfaces of the conductive contact layer, and including a recessed upper surface, wherein the recessed upper surface is recessed to a level lower than that of an upper surface of the conductive contact layer; and
an air gap disposed on the recessed upper surface of the barrier layer and surrounding upper regions of the side surfaces of the conductive contact layer.

13. The semiconductor device of claim 12 , further comprising:
an upper conductive pattern disposed on the contact structure, wherein the upper conductive pattern includes a protruding portion extending between the first spacer structure and the conductive contact layer.

14. The semiconductor device of claim 13 , further comprising:
a separation insulating pattern penetrating the upper conductive pattern to contact the conductive contact layer and the second spacer structure.

15. The semiconductor device of claim 14 , wherein an upper portion of the air gap is capped by the protruding portion of the upper conductive pattern and the separation insulating pattern.

16. The semiconductor device of claim 14 , wherein the recessed upper surface of the barrier layer is at a level lower than that of a lower end of the separation insulating pattern.

17. The semiconductor device of claim 12 , wherein the air gap is disposed between the conductive contact layer and the first spacer structure and between the conductive contact layer and the second spacer structure.

18. A semiconductor device, comprising:
a substrate including an active region, wherein the active region includes a first impurity region and a second impurity region separate from the first impurity region;
a word line structure crossing the active region on the substrate and extending in a first direction;
a bitline disposed on the word line structure, extending in a second direction crossing the first direction, and electrically connected to the first impurity region of the active region;
a spacer structure covering a side surface of the bitline;
a conductive contact layer electrically connected to the second impurity region of the active region on a first region of a side surface of the spacer structure;
an insulating fence disposed on a second region of the side surface of the spacer structure, wherein the insulating fence includes a side surface facing the conductive contact layer;
a barrier layer surrounding a lower region of a lower surface and side surfaces of the conductive contact layer, wherein the barrier layer includes an upper surface recessed to a level lower than that of an upper surface of the conductive contact layer to form a recessed upper surface of the barrier layer;
a first air gap disposed on the recessed upper surface of the barrier layer, surrounding upper regions of the side surfaces of the conductive contact layer, disposed between the conductive contact layer and the spacer structure, and disposed between the conductive contact layer and the insulating fence;
an upper conductive pattern capping an upper portion of the first air gap and contacting the upper surface of the conductive contact layer; and
a da

Assignees

• Samsung Electronics Co Ltd

Inventors

• Ahn Junhyeok
• Lee Kiseok

Classifications

• H10B12/34

  the transistor being at least partially in a trench in the substrate · CPC title

• H10B12/50

  Peripheral circuit region structures · CPC title

• H10D84/0149

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• G11C8/14

  Word line organisation; Word line lay-out · CPC title

• G11C11/4097

  Bit-line organisation, e.g. bit-line layout, folded bit lines · CPC title