Semiconductor device with etched landing pad surface

Patent metadata

Field	Value
Publication number	US-12309996-B2
Application number	US-202217863493-A
Country	US
Kind code	B2
Filing date	Jul 13, 2022
Priority date	Jul 13, 2022
Publication date	May 20, 2025
Grant date	May 20, 2025

Abstract

A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, a bit line, a first isolation spacer, a second isolation spacer, a capacitor contact, a landing pad, and a dielectric structure. The bit line is disposed on the substrate. The first isolation spacer is disposed on a first side of the bit line. The second isolation spacer is disposed on a second side of the bit line. The capacitor contact is disposed on the substrate and spaced apart from the bit line through the first isolation spacer. The landing pad is disposed on the first isolation spacer and electrically connected to the capacitor contact. The dielectric structure is disposed on the second isolation contact. A top surface of the dielectric structure is non-coplanar with a top surface of the landing pad.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
a bit line disposed on the substrate;
a first isolation spacer disposed on a first side of the bit line;
a second isolation spacer disposed on a second side of the bit line;
a capacitor contact disposed on the substrate and spaced apart from the bit line through the first isolation spacer;
a landing pad disposed on the first isolation spacer and electrically connected to the capacitor contact;
a dielectric structure disposed on the second isolation spacer, and
an overlay correction layer disposed on the dielectric structure and the landing pad;
wherein a top surface of the dielectric structure is non-coplanar with a top surface of the landing pad;
wherein the overlay correction layer defines a trench exposing the landing pad, and the overlay correction layer has a first sidewall extending from the landing pad and a second sidewall spaced apart from the landing pad through the first sidewall, and the first sidewall of the overlay correction layer is non-coplanar with the second sidewall of the overlay correction layer.

2. The semiconductor device of claim 1 , wherein the second sidewall of the overlay correction layer is laterally free from overlapping the dielectric structure.

3. The semiconductor device of claim 1 , wherein the second sidewall of the overlay correction layer is steeper than the first sidewall of the overlay correction layer.

4. The semiconductor device of claim 1 , further comprising:
a conductive wire disposed within the trench defined by the overlay correction layer.

5. The semiconductor device of claim 1 , wherein the top surface of the dielectric structure and the top surface of the landing pad collectively define a stepped difference, and a thickness of the overlay correction layer is larger than the stepped difference.

6. The semiconductor device of claim 5 , wherein the stepped difference ranges from about 0.03 times to about 0.5 times the thickness of the overlay correction layer.

7. The semiconductor device of claim 1 , wherein the first isolation spacer comprises an air gap.

8. The semiconductor device of claim 1 , wherein the overlay correction layer has a first top surface and a second top surface lower than the first top surface, and the second top surface of the correction layer extends between a first sidewall and a second sidewall of the overlay correction layer.

9. The semiconductor device of claim 8 , wherein a conductive wire is in contact with the second top surface of the overlay correction layer.

10. A semiconductor device, comprising:
a substrate;
a bit line disposed on the substrate;
a first isolation spacer disposed on a first side of the bit line;
a second isolation spacer disposed on a second side of the bit line;
a capacitor contact disposed on the substrate and spaced apart from the bit line through the first isolation spacer;
a landing pad disposed on the first isolation spacer and electrically connected to the capacitor contact; and
a conductive wire electrically connected to the landing pad,
wherein the conductive wire has a first sidewall connected to the landing pad and a second sidewall spaced apart from the landing pad through the first sidewall, and the first sidewall is non-coplanar with the second sidewall;
wherein the second sidewall of the conductive wire is steeper than the first sidewall of the conductive wire.

11. The semiconductor device of claim 10 , wherein the conductive wire has a surface extending between the first sidewall and the second sidewall of the conductive wire.

12. The semiconductor device of claim 10 , further comprising:
a dielectric structure disposed on the second isolation spacer,
wherein the dielectric structure and the landing pad collectively define a stepped difference.

13. The semiconductor device of claim 12 , further comprising:
an overlay correction layer disposed on the dielectric structure, wherein the overlay correction layer surrounds the conductive wire;
wherein the overlay correction layer has a first sidewall extending from the landing pad and a second sidewall spaced apart from the landing pad through the first sidewall, and the first sidewall of the overlay correction layer is non-coplanar with the second sidewall of the overlay correction layer.

14. The semiconductor device of claim 13 , wherein the overlay correction layer has a first top surface and a second top surface lower than the first top surface, and the second top surface of the correction layer extends between the first sidewall and the second sidewall of the overlay correction layer, and the second sidewall of the overlay correction layer is steeper than the first sidewall of the overlay correction layer.

15. The semiconductor device of claim 13 , wherein the overlay correction layer is in contact with a top surface of the landing pad.

16. The semiconductor device of claim 13 , wherein the first isolation spacer comprises an air gap, and the conductive wire vertically overlaps the air gap of the first isolation spacer.

17. The semiconductor device of claim 13 , wherein a thickness of the overlay correction layer is larger than the stepped difference between the dielectric structure and the landing pad.

Assignees

• Nanya Technology Corp

Inventors

• Chu Yen-Ho

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/098

  by filling between adjacent conductive parts · CPC title

• H10W20/072

  of dielectric parts comprising air gaps · CPC title

• H10W20/46

  comprising air gaps · CPC title

• H10W20/0693

  by forming self-aligned vias · CPC title