Semiconductor memory device and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-11205652-B2
Application number	US-201916506316-A
Country	US
Kind code	B2
Filing date	Jul 9, 2019
Priority date	Dec 24, 2018
Publication date	Dec 21, 2021
Grant date	Dec 21, 2021

Abstract

A semicondcutor memory device may include a substrate, a bit line structure extending in one direction on the substrate, the bit line structure including a sidewall, a storage node contact on the sidewall of the bit line structure, first and second spacers between the sidewall of the bit line structure and the storage node contact, the first spacer separated from the second spacer by a space between the first spacer and the second spacer, an interlayer dielectric layer on the bit line structure, the interlayer dielectric layer including a bottom surface, a spacer capping pattern extending downward from the bottom surface of the interlayer dielectric layer toward the space between the first and second spacers, and a landing pad structure penetrating the interlayer dielectric layer, the landing pad structure coupled to the storage node contact.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a substrate;
a bit line structure extending in one direction on the substrate, the bit line structure including a sidewall;
a storage node contact on the sidewall of the bit line structure;
first and second spacers between the sidewall of the bit line structure and the storage node contact, the first spacer separated from the second spacer by a space between the first spacer and the second spacer;
an interlayer dielectric layer on the bit line structure, the interlayer dielectric layer including a bottom surface;
a spacer capping pattern extending downward from the bottom surface of the interlayer dielectric layer toward the space between the first and second spacers; and
a landing pad structure penetrating the interlayer dielectric layer, the landing pad structure coupled to the storage node contact,
wherein the spacer capping pattern has a width that increases with increasing distance from the bottom surface of the interlayer dielectric layer.

2. The semiconductor memory device of claim 1 , wherein
the first and second spacers define an air spacer therebetween, the air spacer below the spacer capping pattern.

3. The semiconductor memory device of claim 1 , wherein the landing pad structure includes:
a protrusion protruding toward the substrate, the protrusion contacting the spacer capping pattern.

4. The semiconductor memory device of claim 1 , wherein
the landing pad structure includes a protrusion protruding toward the substrate; and
a bottom end of the protrusion is at a vertical level between the bottom surface of the interlayer dielectric layer and a bottom end of the spacer capping pattern.

5. The semiconductor memory device of claim 1 , wherein
the landing pad structure includes a protrusion protruding toward the substrate; and
a bottom end of the protrusion is on one of the first spacer, the second spacer, or the spacer capping pattern.

6. The semiconductor memory device of claim 1 , wherein the landing pad structure includes a flat region in contact with the bottom surface of the interlayer dielectric layer.

7. The semiconductor memory device of claim 1 , wherein
the bit line structure includes a bit line and a bit line capping pattern on the bit line, and
the landing pad structure is in contact with the bit line capping pattern.

8. The semiconductor memory device of claim 1 , wherein a top surface of the landing pad structure is at a same level as a top surface of the interlayer dielectric layer.

9. The semiconductor memory device of claim 1 , wherein a bottom end of the spacer capping pattern is at a higher level than a top surface of the storage node contact.

10. The semiconductor memory device of claim 1 , wherein the spacer capping pattern corresponds to a portion of interlayer dielectric layer that partially fills the space between the first spacer and the second spacer.

11. A semiconductor memory device, comprising:
a substrate including a first active region and a second active region, the first active region and the second active region spaced apart from each other;
a bit line structure coupled to the first active region, the bit line structure running across the substrate, the bit line structure include a sidewall;
a spacer structure on the sidewall of the bit line structure;
an interlayer dielectric layer on the bit line structure and the spacer structure; and
a landing pad structure penetrating the interlayer dielectric layer and electrically connected to the second active region, the landing pad structure including a protrusion protruding toward the substrate, and a bottom end of the protrusion being located at a level lower than a top end of the spacer structure, wherein
the landing pad structure includes a flat region parallel to a top surface of the substrate; and
the flat region is between a bottom surface of the interlayer dielectric layer and a bottom surface of the landing pad structure.

12. The semiconductor memory device of claim 11 , wherein
the bit line structure includes,
a bit line, and
a bit line capping pattern on the bit line, and
the protrusion is in contact with the bit line capping pattern.

13. The semiconductor memory device of claim 11 , wherein a top surface of the landing pad structure is at a same level as a top surface of the interlayer dielectric layer.

14. The semiconductor memory device of claim 11 , wherein the bottom end of the protrusion is on the spacer structure.

15. A semiconductor memory device, comprising:
a substrate;
a pair of bit line structures on the substrate, the pair of bit line structures extending in parallel along one direction;
a storage node contact between the pair of bit line structures;
a lower landing pad between the pair of bit line structures, the lower landing pad on the storage node contact;
an interlayer dielectric layer on the pair of bit line structures and the lower landing pad, the interlayer dielectric layer including a bottom surface; and
an upper landing pad penetrating the interlayer dielectric layer and coupled to the lower landing pad, the upper landing pad having a bottom end at a level lower than the bottom surface of the interlayer dielectric layer,
wherein the bottom end of the upper landing pad is spaced apart from the lower landing pad, and
the bottom end of the upper landing pad is at a lower level than an upper surface of the lower landing pad.

16. The semiconductor memory device of claim 15 , further comprising:
a barrier pattern between the lower landing pad and the pair of bit line structures; and wherein
an uppermost surface of the barrier pattern is at a same level as the bottom surface of the interlayer dielectric layer.

17. The semiconductor memory device of claim 15 , wherein a top surface of the lower landing pad is in contact with the bottom surface of the interlayer dielectric layer.

18. The semiconductor memory device of claim 15 , wherein at least a portion of the upper landing pad vertically overlaps the bit line structure.

19. The semiconductor memory device of claim 15 , wherein a bottom end of the upper landing pad is between the bit line structure and the lower landing pad.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Dongjun
• Shin Sang Chul
• Kim Bong-Soo
• Kim Jiyoung

Classifications

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/072

  of dielectric parts comprising air gaps · CPC title

• H10W20/46

  comprising air gaps · CPC title

• G11C5/063

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title