Semiconductor apparatus and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-12438136-B2
Application number	US-202117536268-A
Country	US
Kind code	B2
Filing date	Nov 29, 2021
Priority date	Mar 12, 2021
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

A semiconductor apparatus and a method for manufacturing the semiconductor apparatus are provided. The semiconductor apparatus includes: a base substrate; a chip arranged on the base substrate, wherein the chip includes a chip main body and a plurality of terminals arranged on the chip main body; a terminal expansion layer arranged on the base substrate, the terminal expansion layer including a conductive material, and the terminal expansion layer and at least one terminal are located on a same side of the chip main body; and a plurality of expansion wires in the terminal expansion layer, wherein the plurality of expansion wires are electrically connected to the plurality of terminals, respectively, to lead out the plurality of terminals, wherein an orthographic projection of at least one expansion wire on the base substrate completely covers an orthographic projection of a terminal electrically connected to the expansion wire on the base substrate.

First claim

What is claimed is:

1. A semiconductor apparatus, comprising:
a base substrate;
a chip arranged on the base substrate, wherein the chip comprises a chip main body and a plurality of terminals arranged on the chip main body;
a terminal expansion layer arranged on the base substrate, wherein the terminal expansion layer comprises a conductive material, and the terminal expansion layer and at least one terminal are located on a same side of the chip main body; and
a plurality of expansion wires in the terminal expansion layer, wherein the plurality of expansion wires are electrically connected to the plurality of terminals, respectively, so as to lead out the plurality of terminals,
wherein an orthographic projection of at least one expansion wire on the base substrate completely covers an orthographic projection of a terminal electrically connected to the expansion wire on the base substrate,
wherein the chip comprises a first chip, a second chip, and a third chip, the first chip, the second chip, and the third chip being configured to implement different functions from each other,
wherein the first chip comprises at least two first terminals, and the second chip comprises at least two second terminals,
wherein the first chip comprises at least one of a light-emitting chip and a sensor chip, and the second chip comprises at least one of a sensor chip and a control chip,
wherein one end of the at least one expansion wire is electrically connected to the first chip, and the other end of the at least one expansion wire is electrically connected to the second chip,
wherein the semiconductor apparatus further comprises at least one chip set, and each of the at least one chip set comprises at least one second chip and at least one third chip, and
wherein a plurality of chip sets are electrically connected to a plurality of first chips in a one-to-one correspondence, or one chip set is electrically connected to the plurality of first chips.

2. The semiconductor apparatus according to claim 1 , wherein the semiconductor apparatus further comprises an adhesive layer arranged between the base substrate and the chip main body, and the adhesive layer is configured to fix the chip to the base substrate; and
wherein the chip main body comprises a first surface facing or in contact with the adhesive layer, and the at least one terminal is arranged on a surface of the chip main body other than the first surface.

3. The semiconductor apparatus according to claim 2 , wherein the base substrate comprises a first base substrate surface, and the chip is arranged on the first base substrate surface; and
wherein the chip main body of the chip comprises a second surface, a first side surface and a second side surface, the second surface and the first surface are located on opposite sides of the chip main body, respectively, the first side surface and the second side surface are located on side surfaces of the chip main body, respectively, and each of the first side surface and the second side surface connects the first surface and the second surface, and
at least one of the first side surface and the second side surface is inclined with respect to the first base substrate surface.

4. The semiconductor apparatus according to claim 3 , wherein the at least one expansion wire is in direct contact with at least one terminal, and a part of the at least one expansion wire is in direct contact with one of the first side surface and the second side surface; or
wherein the plurality of terminals comprised in the chip are each located on the second surface of the chip main body of the chip; or
the plurality of terminals comprised in the chip are located on the first side surface and the second side surface of the chip main body of the chip, respectively; or
the plurality of terminals comprised in the chip are located on the first surface and the second surface of the chip main body of the chip, respectively.

5. The semiconductor apparatus according to claim 2 , wherein the semiconductor apparatus further comprises a first planarization layer which is arranged on a side of the chip and covers the terminal; and
wherein the terminal expansion layer is located on a side of the first planarization layer away from the chip, and an end of the expansion wire is electrically connected to the terminal through a via hole or a groove passing through the first planarization layer; or
wherein the semiconductor apparatus further comprises a spacer located on a side of the chip main body close to the base substrate, and an orthographic projection of the spacer on the base substrate and an orthographic projection of the chip main body on the base substrate at least partially overlap; or
wherein the semiconductor apparatus further comprises a first planarization layer which is arranged on a side of the chip and covers the terminal, and a second planarization layer arranged on a side of the first planarization layer away from the base substrate; and
wherein the semiconductor apparatus further comprises a first wire located in a redistribution layer, and
the redistribution layer is located on a side of the second planarization layer away from the chip, and an end of the first wire is electrically connected to the extension wire through a via hole or groove passing through the first planarization layer and the second planarization layer.

6. The semiconductor apparatus according to claim 1 , wherein the base substrate comprises a first base substrate surface, the chip is arranged on the first base substrate surface, and the first base substrate surface comprises a first base substrate edge; and
wherein the orthographic projection of the at least one expansion wire on the base substrate is inclined with respect to the first base substrate edge.

7. The semiconductor apparatus according to claim 6 , wherein the chip main body has a second surface away from the base substrate, an orthographic projection of the second surface on the base substrate has a regular shape, and the orthographic projection of the second surface on the base substrate comprises a first edge, and
the first edge is inclined with respect to the first base substrate edge.

8. The semiconductor apparatus according to claim 7 , wherein a first angle is formed between an extension line of the orthographic projection of the at least one expansion wire on the base substrate and an extension line of the first base substrate edge, and the first angle is greater than 0° and less than 90°; and/or
a second angle is formed between an extension line of the first edge and the extension line of the first base substrate edge, and the second angle is greater than 0° and less than 90°.

9. The semiconductor apparatus according to claim 1 , wherein the semiconductor apparatus further comprises a functional device electrically connected to at least one terminal of the chip, and
the functional device and the chip are located in different layers.

10. The semiconductor apparatus according to claim 1 , wherein the semiconductor apparatus comprises a plurality of repeating units arranged on the base substrate in an array in a first direction and a second direction; and
wherein each of the plurality of repeating units comprises a plurality of chips, and the plurality of chips in each of the plurality of repeating units are arranged on the base substrate in an array in the first direction and the second direction, or,
at least some of the plurality of chips in each of the plurality of repeating units are arranged on the base substrate in an array in the first direction and the second direction; and

wherein a relative position of at least one chip in one of at least two of the plurality of repeating uni

Assignees

• Boe Technology Group Co Ltd

Inventors

• Wang Meili
• Liang Xuan
• Wang Fei
• Wang Lei
• Yang Yafeng
• Dong Xue
• Cao Zhanfeng
• Wang Mingxing
• Li Fuqiang
• Zhang Chenyang
• Zhao Xinxin
• Han Yanling
• Wang Lei
• Feng Xuan
• Li Yapeng

Classifications

• H10P74/23

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W70/652

  Cross-sectional shapes · CPC title