Semiconductor memory device having an ohmic contact on the impurity regions

Patent metadata

Field	Value
Publication number	US-12432909-B2
Application number	US-202318093561-A
Country	US
Kind code	B2
Filing date	Jan 5, 2023
Priority date	Apr 5, 2022
Publication date	Sep 30, 2025
Grant date	Sep 30, 2025

Abstract

A semiconductor memory device includes an active portion defined by a device isolation pattern, the active portion including a first impurity region located at a center portion of the active portion and a second impurity region located at an end portion of the active portion, a word line provided on the active portion and extending in a first direction, a bit line provided on the word line and extending in a second direction crossing the first direction, a bit line contact provided between the bit line and the first impurity region of the active portion, a storage node pad provided on the second impurity region of the active portion, and a storage node contact provided on the storage node pad and at a side of the bit line.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
an active portion defined by a device isolation pattern, the active portion comprising a first impurity region located at a center portion of the active portion and a second impurity region located at an end portion of the active portion;
a word line provided on the active portion and extending in a first direction;
a bit line provided on the word line and extending in a second direction crossing the first direction;
a bit line contact provided between the bit line and the first impurity region of the active portion;
a storage node pad provided on the second impurity region of the active portion;
a storage node contact provided on the storage node pad and at a side of the bit line; and
an ohmic contact layer provided in at least one of a first region between the first impurity region and the bit line and a second region between the second impurity region and the storage node contact,
wherein the ohmic contact layer comprises a two-dimensional material.

2. The semiconductor memory device of claim 1 , wherein the ohmic contact layer comprises at least one of graphene, transition metal dichalcogenides (TMDC), and black phosphorus (BP).

3. The semiconductor memory device of claim 1 , wherein the bit line contact comprises a metallic material, and
wherein the ohmic contact layer is provided between the first impurity region and the bit line contact.

4. The semiconductor memory device of claim 1 , wherein the bit line contact comprises polysilicon,
wherein the semiconductor memory device further comprises a bit line metal pattern interposed between the bit line contact and the bit line, and
wherein the ohmic contact layer is provided between the bit line contact and the bit line metal pattern.

5. The semiconductor memory device of claim 4 , wherein the bit line metal pattern comprises at least one of tungsten, titanium, aluminum, copper, ruthenium, iridium, and molybdenum.

6. The semiconductor memory device of claim 1 , wherein the storage node pad comprises polysilicon.

7. The semiconductor memory device of claim 6 , wherein the ohmic contact layer is provided between the storage node pad and the storage node contact.

8. The semiconductor memory device of claim 7 , wherein the ohmic contact layer comprises a rounded bottom surface.

9. The semiconductor memory device of claim 1 , wherein the storage node pad comprises a metallic material.

10. The semiconductor memory device of claim 9 , wherein the ohmic contact layer is provided between the storage node pad and the second impurity region.

11. The semiconductor memory device of claim 10 , further comprising a storage node polysilicon pattern provided between the ohmic contact layer and the second impurity region.

12. The semiconductor memory device of claim 10 , wherein the ohmic contact layer is provided to enclose an entire bottom surface of the storage node pad and at least a portion of a side surface of the storage node pad.

13. A semiconductor memory device, comprising:
an active portion defined by a device isolation pattern, the active portion comprising a first impurity region and a second impurity region;
a word line provided on the active portion and extending in a first direction;
a bit line provided on the word line and extending in a second direction crossing the first direction;
a bit line contact provided between the bit line and the first impurity region of the active portion;
a storage node pad provided on the second impurity region of the active portion; and
a storage node contact provided on the storage node pad and at a side of the bit line,
wherein the bit line contact and the storage node pad comprise a metallic material,
wherein the bit line contact is vertically spaced apart from the first impurity region of the active portion, and
wherein the storage node pad is vertically spaced apart from the second impurity region of the active portion.

14. The semiconductor memory device of claim 13 , further comprising:
a first ohmic contact layer provided between the first impurity region of the active portion and the bit line contact; and
a second ohmic contact layer provided between the second impurity region of the active portion and the storage node pad,
wherein the first ohmic contact layer and the second ohmic contact layer comprise at least one of graphene, transition metal dichalcogenides, and black phosphorus.

15. The semiconductor memory device of claim 14 , wherein the metallic material comprises at least one of tungsten, titanium, ruthenium, and molybdenum.

16. The semiconductor memory device of claim 14 , further comprising a storage node polysilicon pattern provided between the second impurity region and the second ohmic contact layer.

17. The semiconductor memory device of claim 14 , wherein the second ohmic contact layer is provided to enclose a entire bottom surface of the storage node pad and at least a portion of a side surface of the storage node pad.

18. A semiconductor memory device, comprising:
a device isolation pattern defining active portions comprising a first impurity region and a second impurity region;
a word line extending in a first direction to cross the active portions;
a bit line vertically overlapping with the first impurity region, the bit line provided on the word line, and extending in a second direction crossing the first direction;
a bit line contact provided between the bit line and the first impurity region;
a bit line capping pattern on the bit line contact;
a storage node pad on the second impurity region;
a first ohmic contact layer on the storage node pad;
a storage node contact provided at a side of the bit line and adjacent to the first ohmic contact layer;
a landing pad on the storage node contact;
a gapfill insulating pattern provided between the storage node pad and the bit line contact; and
a bit line spacer provided between the bit line and the storage node contact,
wherein the first ohmic contact layer comprises at least one of graphene, transition metal dichalcogenides, and black phosphorus.

19. The semiconductor memory device of claim 18 , wherein the bit line contact comprises at least one of tungsten, titanium, ruthenium, and molybdenum.

20. The semiconductor memory device of claim 19 , further comprising a second ohmic contact layer provided between the first impurity region and the bit line contact,
wherein the second ohmic contact layer comprises at least one of graphene, transition metal dichalcogenides, and black phosphorus.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Ahn Junhyeok
• Jeong Woojin
• Kim Hui-Jung

Classifications

• H10B12/482 Primary

  Bit lines · CPC title

• H10B12/488

  Word lines · CPC title

• H10B12/0335

  Making a connection between the transistor and the capacitor, e.g. plug · CPC title

• H10B12/50

  Peripheral circuit region structures · CPC title

• H10B12/053

  the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383) · CPC title