Semiconductor device, method of fabricating the same, and apparatus used in fabrication thereof

Patent metadata

Field	Value
Publication number	US-10361208-B2
Application number	US-201715635725-A
Country	US
Kind code	B2
Filing date	Jun 28, 2017
Priority date	Nov 17, 2014
Publication date	Jul 23, 2019
Grant date	Jul 23, 2019

Abstract

A semiconductor device includes a substrate, upper impurity regions in upper portions of the substrate, metal electrodes electrically connected to the upper impurity regions, metal silicide layers between the metal electrodes and the upper impurity regions, and a lower impurity region in a lower portion of the substrate. A method of fabricating the semiconductor device and an apparatus used in fabricating the semiconductor device is also provided.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate;
upper impurity regions in upper portions of the substrate;
metal electrodes electrically connected to the upper impurity regions;
metal silicide layers between the metal electrodes and the upper, impurity regions;
a lower impurity region in a lower portion of the substrate; and
global buried contacts (GBCs) respectively on the upper impurity regions,
wherein,
the semiconductor device includes a dynamic random access memory (DRAM) device, and
the metal silicide layers are between the GBCs and the metal electrodes, and

impurity ions are concentrated at an interface between the GBCs and the metal silicide layers.

2. The semiconductor device of claim 1 , wherein
the GBCs comprise polysilicon (Poly-Si), and
the metal silicide layers comprises cobalt silicide (CoSi 2 ).

3. The semiconductor device of claim 1 , wherein
the impurity ions are accumulated at the interface between the GBCs and the metal silicide layers.

4. A semiconductor device comprising:
a substrate in which a plurality of active regions are defined;
an upper impurity region in an upper portion of each of the plurality of active regions;
gate lines embedded in the substrate across the plurality of active regions;
a metal electrode electrically connected to the upper impurity region; and
a metal silicide layer between the upper impurity region and the metal electrode, wherein,
the semiconductor device includes a dynamic random access memory (DRAM) device,
a first contact electrically connected to a bit line and a second contact electrically connected to a capacitor are arranged on the upper impurity region,
the metal silicide layer is between the second contact and the metal electrode and
impurity ions are concentrated at an interface between the second contact and the metal silicide layer.

5. The semiconductor device of claim 4 , wherein
the second contact comprises impurity ions, and
the impurity ions are moved to be concentrated at an interface between the second contact and the metal silicide layer.

6. The semiconductor device of claim 4 , wherein
the second contact comprises polysilicon,
the metal silicide layer comprises cobalt silicide, and
the metal electrode is in contact with a lower electrode of the capacitor.

7. The semiconductor device of claim 4 , further comprising a lower impurity region in a lower portion of the substrate.

8. The semiconductor device of claim 4 , wherein
the impurity ions are accumulated at the interface between the second contact and the metal silicide layer.

Assignees

• Cho Choong Rae
• Samsung Electronics Co Ltd

Inventors

• Cho Choong-Rae

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P95/80

  Electrical treatments, e.g. for electroforming · CPC title

• H10P32/1406

  by ion implantation · CPC title

• H10P32/171

  being group IV material · CPC title

• H10D64/0121 Primary

  to Group IV semiconductors · CPC title