Semiconductor device and method for fabricating thereof

Patent metadata

Field	Value
Publication number	US-2022013467-A1
Application number	US-202117358752-A
Country	US
Kind code	A1
Filing date	Jun 25, 2021
Priority date	Jul 13, 2020
Publication date	Jan 13, 2022
Grant date	—

Abstract

A semiconductor device and a method for fabricating the same. The semiconductor device comprising: a first level wiring disposed at a first metal level, and includes a first line wiring, a first insulating capping film and a first side wall graphene film, the first insulating capping film extending along an upper surface of the first line wiring, and the first side wall graphene film extending along a side wall of the first line wiring; an interlayer insulating film covering the side wall of the first line wiring and a side wall of the first insulating capping film; and a second level wiring disposed at a second metal level higher than the first metal level, and includes a second via connected to the first line wiring, and a second line wiring connected to the second via, wherein the second via penetrates the first insulating capping film.

First claim

1 . A semiconductor device comprising:
a first level wiring disposed at a first metal level, the first level wiring including a first line wiring, a first insulating capping film, and a first side wall graphene film, the first insulating capping film extending along an upper surface of the first line wiring, and the first side wall graphene film extending along a side wall of the first line wiring; an interlayer insulating film which covers the side wall of the first line wiring and a side wall of the first insulating capping film; and a second level wiring disposed at a second metal level higher than the first metal level, the second level wiring including a second via connected to the first line wiring, and a second line wiring connected to the second via, wherein the second via penetrates the first insulating capping film.

2 . The semiconductor device of claim 1 , wherein the first level wiring further includes a first bottom graphene film extending along a bottom surface of the first line wiring.

3 . The semiconductor device of claim 1 , wherein the first level wiring further includes a first upper surface graphene film extending along an upper surface of the first line wiring between the first line wiring and the first insulating capping film.

4 . The semiconductor device of claim 1 ,
wherein the second level wiring further includes a second side wall graphene film extending along a side wall of the second line wiring, and a second insulating capping film extending along an upper surface of the second line wiring, and wherein the second line wiring and the second via have an integral structure.

5 .- 6 . (canceled)

7 . The semiconductor device of claim 4 , further comprising:
a third level wiring disposed at a third metal level between the first metal level and the second metal level, the third level wiring including a third line wiring and a third via, the second via being directly connected to the first level wiring.

8 . The semiconductor device of claim 1 ,
wherein the second line wiring includes a wiring filling film, and a wiring barrier film extending along a side wall and a bottom surface of the wiring filling film, wherein the wiring barrier film includes a conductive material including a metal, and wherein a material included in the wiring filling film is different from a material included in the first line wiring.

9 . The semiconductor device of claim 8 , further comprising:
a third level wiring disposed at a third metal level higher than the second metal level, wherein the third level wiring includes a third line wiring connected to the second line wiring, a third insulating capping film extending along an upper surface of the third line wiring, and a third side wall graphene film extending along a side wall of the third line wiring, and wherein the third line wiring includes the same material as the first line wiring.

10 . The semiconductor device of claim 1 , wherein the interlayer insulating film includes an air gap disposed on at least one side of the first level wiring.

11 . The semiconductor device of claim 1 ,
wherein the first level wiring further includes a first via, and wherein the first line wiring and the first via have an integral structure.

12 . The semiconductor device of claim 11 , further comprising:
a substrate disposed below the first level wiring; and a buried power rail at least partially buried inside the substrate, the first via being connected to the buried power rail.

13 . The semiconductor device of claim 1 , wherein the first line wiring includes ruthenium (Ru).

14 .- 15 . (canceled)

16 . A semiconductor device comprising:
a first level wiring disposed at a first metal level, the first level wiring including a first line wiring, a first side wall graphene film, and a first bottom graphene film, the first bottom graphene film extending along a bottom surface of the first line wiring, and the first side wall graphene film extending along a side wall of the first line wiring; and a second level wiring disposed at a second metal level higher than the first metal level, the second level wiring including a second via connected to the first line wiring, and a second line wiring connected to the second via, wherein a thickness of the first side wall graphene film is greater than a thickness of the first bottom graphene film.

17 . (canceled)

18 . The semiconductor device of claim 16 , wherein the first level wiring further includes a first upper surface graphene film extending along an upper surface of the first line wiring.

19 . The semiconductor device of claim 18 , wherein a thickness of the first upper surface graphene film is greater than or equal to a thickness of the first side wall graphene film.

20 . The semiconductor device of claim 16 ,
wherein the second level wiring further includes a second side wall graphene film extending along a side wall of the second line wiring, and a second insulating capping film extending along an upper surface of the second line wiring, and wherein the second line wiring and the second via have an integral structure.

21 . (canceled)

22 . The semiconductor device of claim 16 ,
wherein the second line wiring includes a wiring filling film, and a wiring barrier film extending along a side wall and a bottom surface of the wiring filling film, wherein the wiring barrier film includes a conductive material including a metal, and wherein a material included in the wiring filling film is different from a material included in the first line wiring.

23 . The semiconductor device of claim 22 , wherein the first line wiring includes ruthenium (Ru), and the wiring filling film includes copper (Cu).

24 . A semiconductor device comprising:
a first level wiring disposed at a first metal level, the first level wiring including a first ruthenium line wiring, a first insulating capping film, a first side wall graphene film, and a first bottom graphene film, the first insulating capping film extending along an upper surface of the first ruthenium line wiring, the first side wall graphene film extending along a side wall of the first ruthenium line wiring, and the first bottom graphene film extending along a bottom surface of the first ruthenium line wiring; an interlayer insulating film which covers a side wall of the first ruthenium line wiring and a side wall of the first insulating capping film; and a second level wiring disposed at a second metal level higher than the first metal level, the second level wiring including a second via penetrating the first insulating capping film and connected to the first ruthenium line wiring, and a second line wiring connected to the second via.

25 . The semiconductor device of claim 24 , wherein a thickness of the first side wall graphene film is greater than a thickness of the first bottom graphene film.

26 . The semiconductor device of claim 24 , wherein the first level wiring further includes a first upper surface graphene film which extends along an upper surface of the first ruthenium line wiring, between the first ruthenium line wiring and the first insulating capping film.

27 .- 29 . (canceled)

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Jang Eun
• Lee Min Joo
• Kim Wan Don
• Lee Hyun Bae

Classifications

• H10W20/0633

  using subtractive patterning of the conductive members · CPC title

• H10W20/4437

  the principal metal being a transition metal · CPC title

• H10W20/421

  Skip vias, i.e. vias that do not connect all metallization layers that they pass through · CPC title

• H10W20/438

  Interconnections with multiple fill metals, e.g. having different metals in wide and narrow interconnections, or having different metals in vias and in trenches · CPC title

• H10W20/427

  Power or ground buses · CPC title