Bump structure and method of making the same

Patent metadata

Field	Value
Publication number	US-12431365-B2
Application number	US-202418642173-A
Country	US
Kind code	B2
Filing date	Apr 22, 2024
Priority date	Feb 27, 2020
Publication date	Sep 30, 2025
Grant date	Sep 30, 2025

Abstract

In a method of manufacturing a semiconductor device first conductive layers are formed over a substrate. A first photoresist layer is formed over the first conductive layers. The first conductive layers are etched by using the first photoresist layer as an etching mask, to form an island pattern of the first conductive layers separated from a bus bar pattern of the first conductive layers by a ring shape groove. A connection pattern is formed to connect the island pattern and the bus bar pattern. A second photoresist layer is formed over the first conductive layers and the connection pattern. The second photoresist layer includes an opening over the island pattern. Second conductive layers are formed on the island pattern in the opening. The second photoresist layer is removed, and the connection pattern is removed, thereby forming a bump structure.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a pad electrode disposed over a substrate;
one or more conductive layers disposed over the pad electrode; and
a bump structure disposed over the one or more conductive layers,
wherein the bump structure comprises an under-cut at an interface between the bump structure and an uppermost layer of the one or more conductive layers,
wherein the one or more conductive layers on which the bump structure is formed is surrounded by a ring shaped groove, and
wherein a distance from an edge of the ring shaped groove to a lateral end of the under-cut is greater than a distance from a side face of the bump structure to the lateral end of the under-cut.

2. The semiconductor device of claim 1 , wherein the under-cut is only partially formed and no under-cut is formed at a remaining part between the bump structure and the uppermost layer of the one or more conductive layers.

3. The semiconductor device of claim 1 , wherein at least a part of an uppermost layer of the one or more conductive layers is exposed from the bump structure in plan view.

4. The semiconductor device of claim 1 , wherein:
the bump structure has a rectangular shape in plan view, and
the under-cut is disposed at one side of the rectangular shape.

5. The semiconductor device of claim 1 , wherein the bump structure includes two or more conductive layers.

6. The semiconductor device according to claim 5 , wherein an uppermost one of the two or more conductive layers is a solder layer.

7. The semiconductor device of claim 6 , wherein the solder layer includes at least one selected from the group consisting of AgSn, SnAgCu, PbSn, and CuSn.

8. The semiconductor device according to claim 5 , wherein one of the two or more conductive layers includes Ni.

9. A semiconductor device, comprising:
a pad electrode disposed over a substrate;
an insulating layer disposed over the pad electrode;
one or more conductive layers disposed over the pad electrode and the insulating layer; and
a bump structure disposed over the one or more conductive layers,
wherein the one or more conductive layers on which the bump structure is formed is surrounded by a ring shaped groove, wherein the ring shaped groove exposes the insulating layer, and
wherein a part of the bump structure is formed in the ring shaped groove in contact with the insulating layer and a side face of the one or more conductive layers.

10. The semiconductor device of claim 9 , wherein the bump structure has a rectangular shape in plan view.

11. The semiconductor device of claim 9 , wherein the bump structure includes two or more conductive layers.

12. The semiconductor device according to claim 11 , wherein an uppermost one of the two or more conductive layers is a solder layer.

13. The semiconductor device of claim 12 , wherein the solder layer includes at least one selected from the group consisting of AgSn, SnAgCu, PbSn, and CuSn.

14. The semiconductor device according to claim 11 , wherein one of the two or more conductive layers includes Ni.

15. A semiconductor device, comprising:
a pad electrode disposed over a substrate;
an insulating layer disposed over the pad electrode;
one or more conductive layers disposed over the pad electrode and the insulating layer; and
a bump structure disposed over the one or more conductive layers, wherein:
the bump structure comprises an under-cut at an interface between the bump structure and an uppermost layer of the one or more conductive layers,
wherein the one or more conductive layers on which the bump structure is formed is surrounded by a ring shaped groove, and
wherein the under-cut is asymmetric with respect to a center of the bump structure in plan view.

16. The semiconductor device of claim 15 , wherein at least a part of an uppermost layer of the one or more conductive layers is exposed from the bump structure in plan view.

17. The semiconductor device of claim 15 , wherein:
the bump structure has a rectangular shape in plan view, and
the under-cut is disposed at one side of the rectangular shape.

18. The semiconductor device of claim 15 , wherein the bump structure includes two or more conductive layers.

19. The semiconductor device according to claim 18 , wherein an uppermost one of the two or more conductive layers is a solder layer.

20. The semiconductor device according to claim 18 , wherein one of the two or more conductive layers includes Ni.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lu Wen-Hsiung
• Cheng Ming-Da
• Lin Su-Fei
• Liu Hsu-Lun
• Chan Chien-Pin
• Lin Yung-Sheng

Classifications

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W72/20 Primary

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W70/095

  of vias therein · CPC title