Integrated circuit device

Patent metadata

Field	Value
Publication number	US-12426259-B2
Application number	US-202218148566-A
Country	US
Kind code	B2
Filing date	Dec 30, 2022
Priority date	May 25, 2022
Publication date	Sep 23, 2025
Grant date	Sep 23, 2025

Abstract

An integrated circuit device includes a substrate comprising an active region and a word line trench, a word line extending longitudinally in a first horizontal direction in the word line trench, a buried insulating layer on the word line, a conductive plug on the substrate, and a pad structure on the substrate and having a portion in contact with a top surface of the active region and a portion in contact with the conductive plug. The pad structure includes a conductive pad having a bottom surface in contact with the top surface of the active region and a pad spacer in contact with a sidewall of the conductive pad and protruding beyond an inner sidewall of the word line trench in a second horizontal direction orthogonal to the first horizontal direction such that the pad spacer vertically overlaps a portion of the word line in the word line trench.

First claim

What is claimed is:

1. An integrated circuit device comprising:
a substrate comprising an active region and a word line trench extending longitudinally in a first horizontal direction across the active region;
a word line in the word line trench and extending longitudinally in the first horizontal direction at a vertical level lower than a main surface of the substrate;
a buried insulating layer on the word line in the word line trench;
a conductive plug on the substrate; and
a pad structure on the substrate and having a first portion in contact with a top surface of the active region and a second portion in contact with the conductive plug,
wherein the pad structure comprises:
a conductive pad having a bottom surface in contact with the top surface of the active region and a first sidewall extending along an extension line of an inner sidewall of the word line trench, and
a pad spacer in contact with the first sidewall of the conductive pad and protruding beyond the inner sidewall of the word line trench in a second horizontal direction orthogonal to the first horizontal direction such that the pad spacer vertically overlaps a portion of the word line in the word line trench.

2. The integrated circuit device of claim 1 ,
wherein the conductive pad comprises doped polysilicon, and
the pad spacer comprises doped polysilicon, undoped polysilicon, doped epitaxially grown silicon, or undoped epitaxially grown silicon.

3. The integrated circuit device of claim 1 , wherein an uppermost surface of the buried insulating layer is at a same vertical level as an uppermost surface of the pad structure.

4. The integrated circuit device of claim 1 ,
wherein the pad spacer is on the first sidewall and a top surface of the conductive pad,
an uppermost surface of the buried insulating layer is at a same vertical level as an uppermost surface of the pad spacer, and
an uppermost surface of the conductive pad is closer to the substrate than the uppermost surface of the buried insulating layer.

5. The integrated circuit device of claim 1 , wherein an uppermost surface of the buried insulating layer is closer to the substrate than an uppermost surface of the pad structure.

6. The integrated circuit device of claim 1 , further comprising a gap-fill insulating layer in contact with each of the pad spacer and a top surface of the buried insulating layer,
wherein an uppermost surface of the gap-fill insulating layer is at a same vertical level as an uppermost surface of the pad structure.

7. The integrated circuit device of claim 1 , further comprising a gap-fill insulating layer in contact with each of the pad spacer and a top surface of the buried insulating layer,
wherein the pad spacer is on the first sidewall and a top surface of the conductive pad, and
an uppermost surface of the gap-fill insulating layer is at a same vertical level as an uppermost surface of the pad spacer.

8. The integrated circuit device of claim 1 , further comprising a gate dielectric layer surrounding the word line and the buried insulating layer in the word line trench and between the buried insulating layer and the pad structure,
wherein an uppermost surface of the gate dielectric layer is at a same vertical level as an uppermost surface of the pad structure.

9. The integrated circuit device of claim 1 , further comprising a gate dielectric layer surrounding the word line and the buried insulating layer in the word line trench,
wherein a top surface of the gate dielectric layer is in contact with a bottom surface of the pad spacer.

10. The integrated circuit device of claim 1 ,
further comprising a bit line extending longitudinally in the second horizontal direction on the substrate at a vertical level higher than a vertical level of a top surface of the conductive pad; and
a direct contact electrically connected between the bit line and the active region and spaced apart from the pad structure.

11. An integrated circuit device comprising:
a substrate comprising a plurality of active regions spaced apart from each other and a plurality of word line trenches each extending longitudinally in a first horizontal direction across some of the plurality of active regions;
a plurality of word lines each inside respective ones of the plurality of word line trenches and extending longitudinally in the first horizontal direction at a vertical level lower than a main surface of the substrate;
a plurality of bit lines extending longitudinally in a second horizontal direction perpendicular to the first horizontal direction on the substrate;
a plurality of conductive plugs respectively in spaces between each of the plurality of bit lines and electrically connected to one active region of the plurality of active regions; and
a plurality of pad structures between the substrate and the plurality of conductive plugs,
wherein each of the plurality of pad structures comprises:
a conductive pad having opposite sidewalls in the second horizontal direction and a bottom surface, the bottom surface being in contact with the main surface of the substrate between a pair of word line trenches of the plurality of word line trenches and adjacent to each other, and the opposite sidewalls extending along an extension line of an inner sidewall of each of the pair of word line trenches, and
one or more pad spacers in contact with the opposite sidewalls of the conductive pad and protruding beyond the inner sidewall of each of the pair of word line trenches such that the one or more pad spacers vertically overlaps a portion of a word line of the plurality of word lines inside each of the pair of word line trenches.

12. The integrated circuit device of claim 11 ,
wherein each of the conductive pad and the one or more pad spacers comprises doped polysilicon, and
a doping concentration in the one or more pad spacers is equal to or less than a doping concentration in the conductive pad.

13. The integrated circuit device of claim 11 , further comprising a plurality of buried insulating layers each inside respective ones of the plurality of word line trenches and on the plurality of word lines,
wherein an uppermost surface of each of the plurality of buried insulating layers is at a same vertical level as an uppermost surface of each of the plurality of pad structures.

14. The integrated circuit device of claim 11 , further comprising a plurality of buried insulating layers each inside each of the plurality of word line trenches and on the plurality of word lines,
wherein an uppermost surface of each of the plurality of buried insulating layers is closer to the substrate than an uppermost surface of each of the plurality of pad structures.

15. The integrated circuit device of claim 11 ,
further comprising a plurality of buried insulating layers each inside respective ones of the plurality of word line trenches and on the plurality of word lines; and
a plurality of gap-fill insulating layers on the plurality of buried insulating layers and having opposite sidewalls in contact with a pair of the one or more pad spacers included in a pair of pad structures adjacent to each other among the plurality of pad structures,
wherein an uppermost surface of each of the plurality of gap-fill insulating layers is at a same vertical level as an uppermost surface of each of the plurality of pad structures.

16. The integrated circuit device of claim 11 , wherein, in each of the plurality of pad structures, the one or more pad spacers is on only the opposite sidewalls of the conductive pad among the opposite sidewalls and a top surface of the conduct

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Hyeran
• Ahn Junhyeok
• Lee Kiseok

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W15/01

  Manufacture or treatment · CPC title

• H10W15/00 Primary

  Highly-doped buried regions of integrated devices · CPC title

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10B12/482

  Bit lines · CPC title