Semiconductor device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-10103152-B2
Application number	US-201715634066-A
Country	US
Kind code	B2
Filing date	Jun 27, 2017
Priority date	Aug 17, 2016
Publication date	Oct 16, 2018
Grant date	Oct 16, 2018

Abstract

A Semiconductor device and method for fabricating the same are provided. The method includes forming a trench in a substrate, forming a lower gate metal using a first gas, the lower gate metal burying at least a portion of the trench, forming a barrier metal on the lower gate metal, on the barrier metal, forming an upper gate metal using a second gas different from the first gas and forming a capping film on the gate metal, the capping film filling the trench.

First claim

What is claimed is:

1. A method for fabricating a semiconductor device, comprising:
forming a trench in a substrate;
forming a lower gate metal using a first gas, the lower gate metal being recessed, burying at least a portion of the trench;
forming a barrier material on the lower gate metal;
on the barrier material, forming an upper gate metal using a second gas substantially different from the first gas; and
forming a capping film on the gate metal, the capping film filling the trench,
wherein an effective work function of the upper gate metal is less than an effective work function of the lower gate metal.

2. The method of claim 1 , wherein forming the lower gate metal includes
forming a lower gate thin film using the first gas, and
growing the lower gate metal on the lower gate thin film using a third gas different from the first gas.

3. The method of claim 2 , wherein forming the lower gate metal includes allowing a gate metal precursor to react with the first gas and the third gas, and
a reactivity between the gate metal precursor and the first gas is greater than a reactivity between the gate metal precursor and the third gas.

4. The method of claim 3 , wherein forming an upper gate metal includes forming an upper gate film using the second gas, and
growing the upper gate metal on the upper gate film using the third gas,
wherein the third gas is different from the second gas.

5. The method of claim 3 , wherein the gate metal precursor includes at least one of WF 6 and WCl 6 and the third gas includes H 2 .

6. The method of claim 1 , wherein a resistivity of the upper gate metal is greater than a resistivity of the lower gate metal.

7. The method of claim 1 , wherein the lower gate metal and the upper gate metal comprise tungsten.

8. The method of claim 1 , wherein the first gas includes B 2 H 6 , and the second gas includes SiH 4 .

9. The method of claim 1 , wherein forming the lower gate metal includes
forming a lower barrier material conformally along a bottom surface and a side surface of the trench, and
forming the lower gate metal on the lower barrier material.

10. A method for fabricating a semiconductor device, comprising:
forming a device isolation film for defining an active region in a substrate;
forming a trench in the active region;
forming a gate electrode to bury a portion of the trench, the gate electrode including a lower gate metal, a barrier material, and an upper gate metal;
on the gate electrode, forming a capping film for filling the trench; and
forming a source/drain region in at least one side of the trench,
wherein forming the gate electrode includes,
forming a lower gate metal, by using B 2 H 6 gas,
forming a barrier material on the lower gate metal, and
forming an upper gate metal on the barrier material, by using SiH 4 gas.

11. The method of claim 10 , further comprising:
forming a contact electrically connected with the source/drain region,
wherein a distance between the contact and the lower gate metal is greater than a distance between the contact and the upper gate metal.

12. The method of claim 10 , wherein forming the gate electrode comprises:
forming a lower barrier material along a portion of a sidewall, and a bottom surface of the trench; and
forming a lower gate metal on the lower barrier material,
wherein the lower barrier material and the barrier material comprise a same first material.

13. The method of claim 12 , wherein the first material includes at least one of TiN, TaN, Ti, Ta, Mo and Al.

14. The method of claim 10 , wherein forming the gate electrode includes:
forming a gate insulating film that is conformally formed along a bottom surface and a side surface of the trench; and
on the gate insulating film, forming a gate electrode that fills a portion of the trench.

15. A method for fabricating a semiconductor device on a substrate, comprising:
forming a lower barrier material on a trench of the substrate;
forming a lower gate metal on the lower barrier material using a first gas including B 2 H 6 ;
forming an upper barrier material on the lower gate metal; and
on the upper barrier material, forming an upper gate metal using a second gas different from the first gas, the second gas including SiH 4 .

16. The method of claim 15 , wherein
the substrate has an upper surface,
the lower barrier material has an upper surface,
the lower gate metal has an upper surface
the upper surface of the lower barrier material is lower than the upper surface of the substrate, and
the upper surface of the lower gate metal is lower than the upper surface of the substrate.

17. The method of claim 15 , wherein the forming the lower barrier material and the forming the lower gate metal includes,
etching back a first barrier material film and a lower gate material film.

18. The method of claim 15 , wherein the substrate includes an insulating layer on the trench, the insulating layer including an upper surface, and wherein the forming the upper barrier material includes,
conformally forming the upper barrier metal along the upper surface of the insulating layer and along the upper surface of the lower barrier material.

19. The method of claim 15 , wherein the upper barrier material includes at least one of TiN, TaN, Ti, Ta, Mo, and Al.

20. The method of claim 15 , wherein a resistivity of the upper gate metal is greater than a resistivity of the lower gate metal.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Ji Hoon
• Kim Eun Tae
• Park Seong Hun
• Cho Youn Jae
• Park Hee Sook
• Sohn Woong Hee
• Oh Jin Ho

Classifications

• H01L27/10876 Primary

  Electricity · mapped topic

• H01L27/10891

  Electricity · mapped topic

• H01L27/10855

  Electricity · mapped topic

• H01L27/10814

  Electricity · mapped topic

• H01L29/4236

  Electricity · mapped topic