Memory device

Patent metadata

Field	Value
Publication number	US-9136270-B2
Application number	US-201314027372-A
Country	US
Kind code	B2
Filing date	Sep 16, 2013
Priority date	Oct 26, 2012
Publication date	Sep 15, 2015
Grant date	Sep 15, 2015

Abstract

A device isolation layer of the memory device includes a first insulation layer in a lower portion of a device isolation trench, a second insulation layer in an upper portion of the device isolation trench and a separation layer between the first insulation layer and the second insulation layer. First and second conductive fillers are in the first and second insulation layers and are separated by the separation layer.

First claim

What is claimed is:

1. A memory device comprising:
a substrate having an active region and a field region defining the active region, the field region having a device isolation trench;
a device isolation layer in the device isolation trench of the substrate, the device isolation layer including,
a first insulation layer in a lower portion of the device isolation trench, the first insulation layer having a first conductive filler in a first void,
a second insulation layer in an upper portion of the device isolation trench, the second insulation layer having a second conductive filler in a second void, and
a separation layer between the first insulation layer and the second insulation layer;
a gate structure on the active region of the substrate, the gate structure including a buried gate conductive layer;
an impurity layer on the active region and adjacent to the gate structure; and
a conductive interconnector contacting the impurity layer,
wherein the first and the second conductive fillers include a same material as the buried gate conductive layer.

2. The memory device of claim 1 , wherein the gate structure comprises:
a buried structure on an inner sidewall and a bottom surface of a gate trench of the active region of the substrate, the buried structure including a buried gate insulation layer; and
a capping layer on the buried gate conductive layer, the capping layer filling an upper portion of the gate trench,
wherein the buried gate conductive layer is on the buried gate insulation layer and filling a lower portion of the gate trench.

3. The memory device of claim 2 , wherein the impurity layer is on surface portions of the active region at side portions of the buried structure in order to forma buried channel array transistor (BCAT) on the active region of the substrate.

4. The memory device of claim 2 , wherein the device isolation layer further comprises:
a sidewall oxide layer on an inner sidewall and a bottom surface of the device isolation trench,
wherein the separation layer is on a portion of the sidewall oxide layer and on an upper surface of the first insulation layer, the first insulation layer is defined by the sidewall oxide layer and the separation layer, and the second insulation layer is enclosed by the separation layer.

5. The memory device of claim 4 , wherein the sidewall oxide layer includes:
a lower oxide layer having a first thickness from the bottom surface and the inner sidewall of the device isolation trench;
an upper oxide layer having a second thickness from the inner sidewall of the device isolation trench, the second thickness less than the first thickness; and
a stepped portion between the lower oxide layer and the upper oxide layer.

6. The memory device of claim 4 , wherein the sidewall oxide layer and the separation layer include silicon oxide and the first insulation layer and the second insulation layer include silicon nitride.

7. The memory device of claim 1 , wherein the conductive interconnector contacts the second conductive filler of the device isolation layer.

8. A structure comprising:
a device isolation layer in a device isolation trench of a substrate, the device isolation layer including,
a first insulation layer in a lower portion of the device isolation trench, the first insulation layer having a first conductive filler filling a first void formed therein,
a second insulation layer in an upper portion of the device isolation trench, the second insulation layer having a second conductive filler filling a second void formed therein, and
a separation layer between the first insulation layer and the second insulation layer.

9. The structure of claim 8 , further comprising:
a sidewall oxide layer on an inner sidewall and a bottom surface of the device isolation trench,
wherein the separation layer is on a portion of the sidewall oxide layer and on an upper surface of the first insulation layer, the first insulation layer is defined by the sidewall oxide layer and the separation layer, and the second insulation layer is enclosed by the separation layer.

10. The structure of claim 9 , wherein the sidewall oxide layer comprises:
a lower oxide layer having a first thickness from the bottom surface and the inner sidewall of the device isolation trench;
an upper oxide layer having a second thickness from the inner sidewall of the device isolation trench, the second thickness less than the first thickness; and
a stepped portion between the lower oxide layer and the upper oxide layer.

11. The structure of claim 8 , further comprising:
a substrate having an active region and a field region defining the active region;
a gate structure on the active region of the substrate;
an impurity layer on the active region and adjacent to the gate structure; and
a conductive interconnector contacting the impurity layer,
wherein the device isolation trench is formed in the field region.

12. The structure of claim 11 , wherein the conductive interconnector contacts the second conductive filler of the device isolation layer.

13. The structure of claim 11 , wherein the gate structure comprises:
a buried structure on an inner sidewall and a bottom surface of a gate trench of the active region of the substrate, the buried structure including a buried gate insulation layer;
a buried gate conductive layer on the buried gate insulation layer, the buried gate conductive layer filling a lower portion of the gate trench; and
a capping layer on the buried gate conductive layer, the capping layer filling an upper portion of the gate trench.

14. The structure of claim 13 , wherein:
the sidewall oxide layer and the separation layer include silicon oxide;
the first insulation layer and the second insulation layer include silicon nitride; and
the first and the second conductive fillers include a same material as the buried gate conductive layer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Hyun-Chul
• Kim Jae-Seok
• Park Chan-Hong

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P14/43

  Chemical deposition, e.g. chemical vapour deposition [CVD] · CPC title

• H10W10/0145

  of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence) · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014 Primary

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title