Method for manufacturing a semiconductor device

Patent metadata

Field	Value
Publication number	US-9728617-B2
Application number	US-201514935171-A
Country	US
Kind code	B2
Filing date	Nov 6, 2015
Priority date	Nov 14, 2014
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

A method of manufacturing a semiconductor device includes providing a semiconductor substrate having a main surface and a gate electrode which is within a trench between neighboring semiconductor mesas. The gate electrode is electrically insulated from the neighboring semiconductor mesas by respective dielectric layers. A respective pillar on each of the neighboring semiconductor mesas is formed, leaving an opening between the pillars above the trench. Dielectric contact spacers are formed in the opening along respective pillar side walls to narrow the opening above the gate electrode. A conductor is formed, having an interface with the gate electrode. The interface extends along an extension of the gate electrode, and the conductor has a conductivity greater than the conductivity of the gate electrode.

First claim

The invention claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
providing a semiconductor substrate comprising a main surface and a gate electrode which is within a trench between neighboring semiconductor mesas, wherein the gate electrode is electrically insulated from the neighboring semiconductor mesas by a gate trench dielectric;
forming a respective pillar on each of the neighboring semiconductor mesas leaving an opening between the pillars above the trench;
forming dielectric contact spacers in the opening along respective pillar side walls to narrow the opening above the gate electrode; and
after forming the dielectric contact spacers,
forming a conductor having an interface with the gate electrode, the interface extending along an extension of the gate electrode, wherein the conductor has a conductivity greater than the conductivity of the gate electrode,
removing the pillars on each of the neighboring semiconductor mesas after forming the conductor so as to expose a top surface of the neighboring semiconductor mesas, and
depositing a conformal dielectric layer that contacts the exposed top surface of the neighboring semiconductor mesas, the dielectric contact spacers and the conductor.

2. The method of claim 1 , further comprising:
etching a recess into a top surface of the gate electrode before forming the conductor, and
using the dielectric contact spacers as an etch mask.

3. The method of claim 1 , wherein the pillars are formed after the gate electrode is provided.

4. The method of claim 1 , further comprising:
forming an electrical contact which is self-aligned with respect to the neighboring semiconductor mesas and electrically contacts at least one of the neighboring semiconductor mesas, wherein the electrical contact is insulated from the conductor.

5. The method of claim 4 , further comprising:
before forming the electrical contact,
masking a region between the dielectric contact spacers above the conductor.

6. The method of claim 4 , wherein forming the electrical contact comprises depositing a conductive material onto the exposed top surface of the at least one of the semiconductor mesas.

7. The method of claim 1 , wherein the conductor is formed such that a top surface of the conductor is in the opening between the dielectric contact spacers.

8. The method of claim 1 , wherein the conductor is formed such that the conductor extends from below the main surface to above the main surface.

9. The method of claim 1 , wherein in a normal projection onto the main surface, the conductor is formed within the gate electrode, and wherein, in the normal projection, the narrowed opening, after the formation of the dielectric contact spacers, is within the gate electrode.

10. The method of claim 1 , wherein forming the conductor comprises depositing a material forming the conductor, optionally followed by etching a portion of the material forming the conductor.

11. The method of claim 1 , wherein forming the conductor comprises forming at least one of a metal, a metal alloy, a metal nitride, a metal silicide, and a combination thereof.

12. The method of claim 1 , wherein the conformal dielectric layer forms a recess above the conductor, the method further comprising filling the recess with a further dielectric material.

13. The method of claim 12 , wherein filling the recess with the further dielectric material comprises forming a second dielectric layer on the first dielectric layer, the method further comprising:
etching the first and second dielectric layers such that a portion of the top surface of the neighboring semiconductor mesas is exposed from the first and second dielectric layers; and
depositing a conductive material such that the conductive material directly contacts the portion of the top surface of the neighboring semiconductor mesas and is electrically insulated from the conductor by portions of the first and second dielectric layers.

14. The method of claim 1 , wherein the pillars and the dielectric contact spacers are formed such that outer edges of the dielectric contact spacers that adjoin the pillars are disposed over the gate trench dielectric and are laterally spaced apart from sidewalls of the trench at the main surface.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Poelzl Martin

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10D64/01324

  characterised by the sectional shape, e.g. T or inverted-T · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10P14/40 Primary

  of conductive or resistive materials · CPC title

• H01L21/76897

  Electricity · mapped topic