Neural network apparatus

Patent metadata

Field	Value
Publication number	US-12423563-B2
Application number	US-202117238403-A
Country	US
Kind code	B2
Filing date	Apr 23, 2021
Priority date	Oct 8, 2020
Publication date	Sep 23, 2025
Grant date	Sep 23, 2025

Abstract

A neural network apparatus includes: a plurality of memory cells each comprising a variable resistance element and a first transistor; a plurality of bit lines extending in a first direction; and a plurality of word lines extending in a second direction, crossing the bit lines and respectively connected to the first transistor of the plurality of memory cells; a plurality of sub-column circuits each comprising memory cells of the memory cells connected in parallel along the first direction; and a column circuit comprising two or more of the sub-column circuits connected in series along the second direction, wherein, when a neural network operation is performed, the column circuit outputs a summation current to a bit line connected to the column circuit based on voltage applied to the plurality of word lines.

First claim

What is claimed is:

1. A neural network apparatus comprising:
a plurality of memory cells each comprising a variable resistance element and a first transistor;
a plurality of bit lines extending in a first direction; and
a plurality of word lines extending in a second direction, crossing the bit lines and respectively connected to the first transistor of the plurality of memory cells;
a plurality of sub-column circuits each comprising memory cells of the memory cells connected in parallel along the first direction; and
a column circuit comprising two or more of the sub-column circuits connected in series along the second direction between first transistors of one of the sub-column circuits and variable resistance elements of another one of the sub-column circuits,
wherein, when a neural network operation is performed, the column circuit outputs a summation current to a bit line connected to the column circuit based on voltage applied to memory cells of a plurality of the sub-column circuits through the plurality of word lines.

2. The apparatus of claim 1 , wherein a composite resistance value of the column circuit is greater than a composite resistance value of the sub-column circuit.

3. The apparatus of claim 1 , wherein variable resistance elements included in memory cells that share one word line in the column circuit have a same resistance value.

4. The apparatus of claim 1 , further comprising:
a second transistor configured to connect adjacent sub-column circuits from among the two or more sub-column circuits to each other,
wherein the second transistor is configured to:
connect the adjacent sub-column circuits to each other when the neural network operation is performed, and
block connection of the adjacent sub-column circuits when a reading or writing operation is performed on the plurality of memory cells.

5. The apparatus of claim 1 , wherein the neural network apparatus is configured to perform a writing operation on one of memory cells sharing one word line in the column circuit by:
applying different voltages to both ends of the one memory cell; and
applying a same voltage to both ends of the remaining memory cells.

6. The apparatus of claim 1 , wherein, when a reading or writing operation is performed on the plurality of memory cells, one of memory cells sharing one word line in the column circuit stores a weight value for the neural network operation, and remaining memory cells of the memory cells sharing the one word line perform a reading or writing operation.

7. The apparatus of claim 6 , wherein, when the neural network operation is performed, the weight value stored in the one memory cell is spread to the remaining memory cells such that variable resistance elements included in the memory cells sharing one word line in the column circuit have a same resistance value.

8. The apparatus of claim 1 , wherein memory cells included in each of sub-column circuits adjacent to each other in the second direction from among the two or more sub-column circuits have a symmetric arrangement structure.

9. The apparatus of claim 1 , further comprising a source line configured to apply a source voltage to the column circuit, wherein a difference between the source voltage applied to the source line and a voltage applied to the bit line is less than a magnitude of a voltage that varies a resistance value of the variable resistance element.

10. The apparatus of claim 1 , wherein the variable resistance element comprises a magnetic tunnel junction (MTJ) element.

11. The apparatus of claim 1 , wherein the plurality of word lines extend side by side in the second direction.

12. A neural network apparatus comprising:
a plurality of word lines extending in a direction and connected to a column circuit; and
the column circuit, wherein
the column circuit comprises a bit line extending in another direction, and a plurality of sub-column circuits connected in series along the direction between first transistors of one of the sub-column circuits and variable resistance elements of another one of the sub-column circuits, each sub-column circuit comprising a plurality of magnetoresistive random-access memory (MRAM) cells connected in parallel along the other direction; and
the column circuit is configured to output a summation current to the bit line based on voltage applied to MRAM cells of a plurality of the sub-column circuits through the plurality of word lines.

13. The apparatus of claim 12 , wherein
the column circuit comprises a transistor configured to connect adjacent sub-column circuits of the sub-column circuits in series along the direction, and
to write data to an MRAM cell of the MRAM cells, a first voltage is applied to turn off the transistor, a second voltage is applied to one of the word lines connected to the MRAM cell to turn on a transistor of the MRAM cell, and a third voltage is applied to the bit line.

14. The apparatus of claim 12 , wherein
a first MRAM cell of the MRAM cells included in one of the sub-columns and a second MRAM cell of the MRAM cells included in another one of the sub-columns are connected in series by a shared end, and
to write data to the first MRAM cell, a first voltage is applied to another end of the first MRAM cell, a second voltage is applied to the shared end, and the second voltage is applied to another end of the second MRAM cell.

15. The apparatus of claim 12 , wherein a multiply-accumulate (MAC) result is generated based at least in part on the output summation current.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jung Seungchul
• Lee Hyungwoo
• Myung Sungmeen
• Ju Yongmin

Classifications

• G11C11/1655

  Bit-line or column circuits · CPC title

• G06N3/065 Primary

  Analogue means · CPC title

• G06F7/5443 Primary

  Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00) · CPC title

• G06N3/045

  Combinations of networks · CPC title

• G06N3/08

  Learning methods · CPC title