Semiconductor memory device including a correcting circuit

Patent metadata

Field	Value
Publication number	US-10658063-B2
Application number	US-201816123558-A
Country	US
Kind code	B2
Filing date	Sep 6, 2018
Priority date	Oct 26, 2017
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

According to one embodiment, a semiconductor memory device includes a memory cell, a read circuit, a correcting circuit and a write circuit. The read circuit is configured to read first data from the memory cell by receiving a first command. The correcting circuit is configured to generate second data by correcting an error included in the first data. The write circuit is configured to write the second data to the memory cell in response to receiving a second command.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
first and second memory cells;
a read circuit configured to read first data from the first memory cell by receiving a first command;
a correcting circuit configured to generate second data by correcting an error included in the first data;
a storage circuit configured to store third data and the second data by receiving a second command; and
a write circuit configured to, in response to receiving a third command, perform a first writing for writing the second data to the first memory cell, and to perform a second writing for writing the third data to the second memory cell,
wherein the first writing and the second writing are started in parallel in response to receiving the third command.

2. The semiconductor memory device according to claim 1 , wherein the first writing and the second writing are started by a same signal that is generated in response to receiving the third command.

3. The semiconductor memory device according to claim 1 , wherein:
in the second writing, fourth data held in the read circuit and the third data are compared,
in a case where the fourth data and the third data match, the write circuit does not write the third data to the second memory cell, and
in a case where the fourth data and the third data do not match, the write circuit writes the third data to the second memory cell.

4. The semiconductor memory device according to claim 1 , further comprising bit lines, source lines, and a word line that are electrically coupled to the first and second memory cells,
wherein:
a fourth command is received prior to receiving the first command, and
the word line is selected based on the fourth command.

5. The semiconductor memory device according to claim 4 , wherein:
the first command includes a read command selecting the bit lines and the source lines,
the second command includes a write command selecting the bit lines and the source lines, and
the third command includes a pre-charge command setting the bit lines, the source lines, and the word line to a non-selected state.

6. The semiconductor memory device according to claim 1 , wherein:
the correcting circuit detects and corrects an error with respect to the first data, and
in a case where an error is not detected in the first data, in response to receiving the third command, the write circuit does not write the first data to the first memory cell.

7. The semiconductor memory device according to claim 1 , wherein:
the correcting circuit detects and corrects an error with respect to the first data, and
in a case where an error is not detected in the first data, in response to receiving the third command, the write circuit writes the first data to the first memory cell.

8. The semiconductor memory device according to claim 1 , wherein the first and second memory cells are resistance change elements capable of storing data.

Assignees

• Toshiba Memory Corp

Inventors

• Noro Hiromi
• Tsuchida Kenji

Classifications

• G11C11/1673

  Reading or sensing circuits or methods · CPC title

• G11C11/161

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• G11C11/1693

  Timing circuits or methods · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G11C2029/0411

  Online error correction · CPC title