Semiconductor memory device with correcting resistances in series with memory array signal lines

Patent metadata

Field	Value
Publication number	US-10593375-B2
Application number	US-201815914687-A
Country	US
Kind code	B2
Filing date	Mar 7, 2018
Priority date	Sep 15, 2017
Publication date	Mar 17, 2020
Grant date	Mar 17, 2020

Abstract

According to one embodiment, a semiconductor storage device comprises a first memory cell including a first resistance change element; a first bit line and a first source line coupled to the first memory cell; and a first resistance coupled to at least one of the first bit line and the first source line.

First claim

What is claimed is:

1. A semiconductor storage device comprising:
a first memory cell including a first resistance change element;
a second memory cell including a second resistance change element;
a first column selection transistor;
a second column selection transistor;
a first bit line coupled between a first terminal of the first memory cell and a first terminal of the first column selection transistor, and between a first terminal of the second memory cell and the first terminal of the first column selection transistor;
a first source line coupled between a second terminal of the first memory cell and a first terminal of the second column selection transistor, and between a second terminal of the second memory cell and the first terminal of the second column selection transistor; and
a first correcting resistance coupled in series between the first column selection transistor and the second column selection transistor,
wherein the first memory cell and the second memory cell are coupled in parallel to the first correcting resistance.

2. The device of claim 1 , further comprising:
a third memory cell including a third resistance change element;
a fourth memory cell including a fourth resistance change element;
a third column selection transistor;
a fourth column selection transistor;
a second bit line coupled between a first terminal of the third memory cell and a first terminal of the third column selection transistor, and between a first terminal of the fourth memory cell and the first terminal of the third column selection transistor;
a second source line coupled between a second terminal of the third memory cell and a first terminal of the fourth column selection transistor, and between a second terminal of the fourth memory cell and the first terminal of the fourth column selection transistor; and
a second correcting resistance coupled in series between the third column selection transistor and the fourth column selection transistor, and having a resistance value different from the first correcting resistance,
wherein a second terminal of the first column selection transistor is coupled to a second terminal of the third column selection transistor, and
wherein a second terminal of the second column selection transistor is coupled to a second terminal of the fourth column selection transistor.

3. The device of claim 2 , wherein:
the first memory cell further includes a first transistor;
the third memory cell further includes a third transistor;
a control terminal of the first transistor and a control terminal of the third transistor are coupled to a first word line;
the first correcting resistance and the second correcting resistance are configured to minimize a variation between a first sum of resistance values of the first correcting resistance, the first memory cell, the first bit line, and the first source line and a second sum of resistance values of the second correcting resistance, the third memory cell, the second bit line, and the second source line.

4. The device of claim 3 , further comprising:
a fifth memory cell including a fifth resistance change element and a fourth transistor;
a third bit line coupled to a first terminal of the fifth memory cell;
a third source line coupled to a second terminal of the fifth memory cell; and
a third correcting resistance coupled to one of the third bit line and the third source line,
wherein:
the first word line is coupled to a control terminal of the fourth transistor,
the first memory cell is disposed between the third memory cell and the fifth memory cell along the first word line, and
the first correcting resistance has a resistance value smaller than the second correcting resistance and the third correcting resistance or larger than the second correcting resistance and the third correcting resistance.

5. The device of claim 1 , wherein the first correcting resistance is coupled to the first bit line, and is coupled in series between the first memory cell and a sense amplifier, and is coupled in series between the second memory cell and the sense amplifier.

6. The device of claim 1 , wherein the first correcting resistance is coupled to the first source line, is coupled in series between the first memory cell and a sink, and is coupled in series between the second memory cell and the sink.

7. A semiconductor storage device comprising:
a first memory cell including a first resistance change element;
a second memory cell including a second resistance change element;
a first column selection transistor;
a second column selection transistor;
a first bit line coupled between a first terminal of the first memory cell and a first terminal of the first column selection transistor, and between a first terminal of the second memory cell and the first terminal of the first column selection transistor;
a first source line coupled between a second terminal of the first memory cell and a first terminal of the second column selection transistor, and between a second terminal of the second memory cell and the first terminal of the second column selection transistor; and
a first variable resistance circuit coupled in series between the first column selection transistor and the second column selection transistor,
wherein the first memory cell and the second memory cell are coupled in parallel to the first variable resistance circuit.

8. The device of claim 7 , wherein:
the first variable resistance circuit includes a first series circuit and a second series circuit coupled in parallel,
the first series circuit includes a first correcting resistance and a first fuse coupled in series, and
the second series circuit includes a second correcting resistance and a second fuse coupled in series.

9. The device of claim 7 , wherein:
the first variable resistance circuit includes a first series circuit and a second series circuit coupled in parallel,
the first series circuit includes a first correcting resistance and a first transistor coupled in series, and
the second series circuit includes a second correcting resistance and a second transistor coupled in series.

10. The device of claim 7 , wherein the first variable resistance circuit is coupled to the first bit line, is coupled in series between the first memory cell and a sense amplifier, and is coupled in series between the second memory cell and the sense amplifier.

11. The device of claim 7 , wherein the first variable resistance circuit is coupled to the first source line, is coupled in series between the first memory cell and a sink, and is coupled in series between the second memory cell and the sink.

12. A semiconductor storage device comprising:
a first memory cell including a first resistance change element and a first transistor;
a first word line coupled to a control terminal of the first transistor; and
a first correcting resistance coupled to the first word line,
wherein the first correcting resistance includes a first terminal coupled to the first memory cell and a second terminal coupled to a row decoder.

13. The device of claim 12 , further comprising:
a second memory cell including a second resistance change element and a second transistor;
a second word line coupled to a control terminal of the second transistor; and
a second correcting resistance coupled to the second word line and having a resistance value different from the first correcting resistance,
wherein the second correcting resistance includes a first terminal coupled to the second memory cell and a second terminal coupled to the row decoder.

Assignees

• Toshiba Memory Corp

Inventors

• Ishii Kazuyo

Classifications

• G11C13/0023

  Address circuits or decoders · CPC title

• G11C13/0069

  Writing or programming circuits or methods · CPC title

• G11C11/1653 Primary

  Address circuits or decoders · CPC title

• G11C8/10

  Decoders · CPC title

• G11C11/1659

  Cell access · CPC title