Memory devices and methods for operating the same

Patent metadata

Field	Value
Publication number	US-11119674-B2
Application number	US-201916279494-A
Country	US
Kind code	B2
Filing date	Feb 19, 2019
Priority date	Feb 19, 2019
Publication date	Sep 14, 2021
Grant date	Sep 14, 2021

Abstract

A memory device includes an array of composite memory units. At least one of the composite memory units comprises a first memory cell of a first type, a second memory cell of a second type, a first intra-unit data path connecting the first memory cell to the second memory cell, and a first data path control switch. The first data path control switch is responsive to a data transfer enable signal which enables data transfer between the first memory cell and the second memory cell through the first intra-unit data path.

First claim

What is claimed is:

1. A memory device, comprising:
a plurality of composite memory units arranged in rows and columns, at least one of the plurality of composite memory units comprising a first memory cell, a second memory cell, and a first intra-unit data path connecting the first memory cell to the second memory cell, wherein the first memory cell is of a first type and the second memory cell is of a second type,
wherein at least one of the plurality of composite memory units further comprises a first data path control switch, wherein the first data path control switch is responsive to a data transfer enable signal to enable data transfer between the first memory cell and the second memory cell through the first intra-unit data path;
a signal control circuitry, the signal control circuitry asserting data transfer enable signals to first data path control switches in the plurality of composite memory units;
a set of source lines, source bit lines in the set of source lines connecting second memory cells in respective columns of composite memory units to the signal control circuitry; and
control circuits arranged to perform sum-of-products operations and storing results in a selected composite memory unit comprising a first memory cell storing a weight, a second memory cell, a first intra-unit data path, a first data path control switch, the control circuits configured to perform, in coordination, to accomplish the sum-of-products operations and storing results, the steps of:
precharging a first bit line coupled to the first memory cell with a signal representing an input;
applying a row select voltage to a first word line coupled to the first memory cell; and
applying the row select voltage to a second word line coupled to the second memory cell;
asserting a data transfer enable signal to the first data path control switch; and
applying an activating voltage to a first source line coupled to the second memory cell to store a product of the input and the weight in the second memory cell.

2. A method of performing sum-of-products operations and storing results in a composite memory unit, the composite memory unit comprising a first memory cell of a first type storing a weight, a second memory cell of a second type, a first intra-unit data path connecting the first memory cell to the second memory cell, and a first data path control switch responsive to a data transfer enable signal to enable data transfer between the first memory cell and the second memory cell through the first intra-unit data path, wherein the first memory cell coupled to a first word line and a first bit line, and the second memory cell coupled to a second word line, a second bit line and a first source line, the method comprising:
precharging the first bit line of the first memory cell with a signal representing an input;
applying a row select voltage to the first word line of the first memory cell;
applying the row select voltage to the second word line of the second memory cell;
asserting the data transfer enable signal to the first data path control switch; and
applying an activating voltage to the first source line of the second memory cell to store a product of the input and the weight in the second memory cell.

3. The method of claim 2 , further comprising sensing current at the first bit line of the first memory cell, the current representing the product of the input and the weight.

Assignees

• Macronix Int Co Ltd

Inventors

• Chang Hung-Sheng
• Hu han-wen

Classifications

• G06N3/045

  Combinations of networks · CPC title

• G06N3/0464

  Convolutional networks [CNN, ConvNet] · CPC title

• G06F13/1668

  Details of memory controller · CPC title

• G06F7/5443 Primary

  Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00) · CPC title

• G06F13/4022 Primary

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title