2D and 3D sum-of-products array for neuromorphic computing system

Patent metadata

Field	Value
Publication number	US-10957392-B2
Application number	US-201816233404-A
Country	US
Kind code	B2
Filing date	Dec 27, 2018
Priority date	Jan 17, 2018
Publication date	Mar 23, 2021
Grant date	Mar 23, 2021

Abstract

An array of variable resistance cells based on a programmable threshold transistor and a resistor connected in parallel is described, including 3D and split gate variations. An input voltage applied to the transistor, and the programmable threshold of the transistor, can represent variables of sum-of-products operations. Programmable threshold transistors in the variable resistance cells comprise charge trapping memory transistors, such as floating gate transistors or dielectric charge trapping transistors. The resistor in the variable resistance cells can comprise a buried implant resistor connecting the current-carrying terminals (e.g. source and drain) of the programmable threshold transistor. A voltage sensing sense amplifier is configured to sense the voltage generated by the variable resistance cells as a function of an applied current and the resistance of the variable resistance cells.

First claim

What is claimed is:

1. A device, comprising a plurality of levels of word lines overlying a substrate, a plurality of vertical channel structures orthogonal to the substrate, extending through the plurality of levels of word lines, an array of variable resistance cells disposed at cross points of word lines in the plurality of levels of word lines and vertical channel structures in the plurality of vertical channel structures, the array of variable resistance cells being arranged in a plurality of vertical serially-connected strings of variable resistance cells along vertical channel structures in the plurality of vertical channel structures, at least some of the variable resistance cells in the array each comprising a programmable threshold transistor and a resistor connected in parallel; and
circuitry to apply current to a selected vertical channel structure in the plurality of vertical channel structures, and input voltages representing values X 1 to X m of an input vector, where m is at least 3, in parallel to word lines WL 1 to WL m in the plurality of levels of word lines, and
sense amplifier circuits configured for connection to the selected vertical channel structure in the plurality of vertical channel structures, which are responsive to voltage generated by the current and to a sum of variable resistances of a vertical serially-connected string of variable resistance cells along the selected vertical channel structure generated by the input voltages representing values X 1 to X m and weights stored in the variable resistance cells to produce sum-of-products results for the selected vertical channel structure.

2. The device of claim 1 , including word line drivers connected to the word lines in the plurality of levels of word lines to apply variable gate voltages as the input voltages representing values X 1 to X m to the programmable threshold transistors in the variable resistance cells.

3. The device of claim 1 , wherein the programmable threshold transistor in the variable resistance cell is a charge trapping memory transistor.

4. The device of claim 3 , wherein the resistor in the variable resistance cell is a buried implant resistor in the charge trapping memory transistor.

5. The device of claim 1 , wherein the programmable threshold transistor in the variable resistance cell is a floating gate charge trapping memory transistor, and the resistor in the variable resistance cell is a buried implant resistor in the floating gate charge trapping memory transistor.

6. The device of claim 1 , wherein the programmable threshold transistor in the variable resistance cell is a dielectric charge trapping memory transistor, and the resistor in the variable resistance cell is a buried implant resistor in the dielectric charge trapping memory transistor.

7. The device of claim 1 , wherein the at least some of the variable resistance cells in the array each consists of one transistor having a layout footprint, and one resistor, in which the resistor is implemented within the layout footprint of the one transistor.

8. A device, comprising:
a plurality of levels of word lines overlying a substrate;
a plurality of vertical strings of variable resistance cells orthogonal to the substrate, extending through the levels of word lines;
variable resistance cells in at least some of the strings in the plurality of vertical strings each having a first current-carrying node in a corresponding vertical channel structure of the plurality of vertical strings, a second current-carrying node in the corresponding vertical channel structure, and a control terminal in a corresponding word line of the plurality of levels of word lines, and comprising a programmable threshold transistor and a resistor connected in parallel to the first and second current-carrying nodes, the programmable threshold transistor having a gate connected to the control terminal; and wherein:
a variable resistance of each of the variable resistance cells in the strings is a function of a voltage applied to the control gate of the cell, a threshold of the programmable threshold transistor, and the resistor; and including
circuitry to apply current to a selected vertical string in the plurality of vertical strings, and input voltages representing values X 1 to X m of an input vector, where m is at least 3, in parallel to word lines WL 1 to WL m in the plurality of levels of word lines, and
sense amplifier circuits configured for connection to the selected vertical string in the plurality of vertical strings, which are responsive to voltage generated by the current and to a sum of variable resistances of the variable resistance cells along the selected vertical string generated by the input voltages representing values X 1 to X m and weights stored in the variable resistance cells to produce sum-of-products results for the selected vertical string.

9. The device of claim 8 , wherein the programmable threshold transistor in each of the variable resistance cells is a charge trapping memory transistor, and the threshold of the transistor is a function of charge trapped in the charge trapping memory transistor.

10. The device of claim 9 , wherein the resistor in each of the variable resistance cells is a buried implant resistor in the charge trapping memory transistor.

11. The device of claim 8 , including circuitry to program the threshold of the programmable threshold transistor with multiple levels.

12. The device of claim 8 , wherein the programmable threshold transistor in the variable resistance cell is a floating gate charge trapping memory transistor, and the resistor in each of the variable resistance cells is a buried implant resistor in the floating gate charge trapping memory transistor, and the threshold of the transistor is a function of charge trapped in the floating gate charge trapping memory transistor.

13. The device of claim 8 , wherein the programmable threshold transistor in the variable resistance cell is a dielectric charge trapping memory transistor, and the resistor in each of the variable resistance cells is a buried implant resistor in the dielectric charge trapping memory transistor, and the threshold of the transistor is a function of charge trapped in the dielectric charge trapping memory transistor.

Assignees

• Macronix Int Co Ltd

Inventors

• Lee Feng-Min
• Lin Yu-Yu

Classifications

• G06N3/065

  Analogue means · CPC title

• H10D30/681

  having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688) · CPC title

• H10D30/69

  IGFETs having charge trapping gate insulators, e.g. MNOS transistors · CPC title

• G06F7/388

  using other various devices such as electro-chemical, microwave, surface acoustic wave, neuristor, electron beam switching, resonant, e.g. parametric, ferro-resonant · CPC title

• G06F2207/4802

  Special implementations · CPC title