Silicon carbide semiconductor device and method for manufacturing the silicon carbide semiconductor device

Patent metadata

Field	Value
Publication number	US-2016133741-A1
Application number	US-201514929742-A
Country	US
Kind code	A1
Filing date	Nov 2, 2015
Priority date	Nov 6, 2014
Publication date	May 12, 2016
Grant date	—

Abstract

A silicon carbide semiconductor device includes a MOSFET and a peripheral high-breakdown-voltage structure. A source region has a first recess. Trenches extend from the bottom of the first recess. A gate insulating film has an extension the shape of which follows the shape of the first recess. The surface of a gate electrode is positioned to be flush with or below the upper surface of the extension.

First claim

What is claimed is:

1 . A silicon carbide semiconductor device comprising:
a MOSFET including
a substrate of a first or second conductivity type comprising silicon carbide,
a drift layer of a first conductivity type comprising silicon carbide, the drift layer being disposed on the substrate and having an impurity concentration lower than the impurity concentration of the substrate,
a base region of a second conductivity type comprising silicon carbide, the base region being disposed on the drift layer in a cell region,
a source region of a first conductivity type comprising silicon carbide, the source region being disposed on the base region and having an impurity concentration higher than the impurity concentration of the drift layer,
a plurality of trenches, each of the trenches extending in a longitudinal direction and being deeper than the source region and the base region to reach the drift layer, the source region and the base region being disposed on both sides of the trenches,
a deep layer of a second conductivity type, the deep layer being disposed in surface portions of the drift layer under the base region between two adjacent trenches, the bottoms of the deep layer being disposed below the bottom of each of the trenches,
a gate insulating film disposed on the surface of each of the trenches,
a gate electrode disposed on the gate insulating film in each of the trenches,
an interlayer insulating film covering the gate electrode and the gate insulating film, the interlayer insulating film having a contact hole,
a source electrode electrically connected to the source region and the base region through the contact hole, and
a drain electrode disposed on the back side of the substrate; and
a peripheral high-breakdown-voltage structure including second-conductivity-type impurity layers at the bottom of a recessed mesa structure disposed on a peripheral region surrounding the cell region, the mesa structure being deeper than the source region and the base region to reach the drift layer, wherein the source region has a first recess, each of the trenches extends from the bottom of the first recess, the gate insulating film has an extension following the shape of the first recess, and the top surface of the gate electrode is flush with or below the top surface of the extension.

2 . The silicon carbide semiconductor device according to claim 1 wherein a cap oxide film is formed by oxidation of the gate electrode and the top surface of the cap oxide film of the gate electrode is flush with or below the top surface of the extension.

3 . The silicon carbide semiconductor device according to claim 1 wherein the MOSFET is an inverted-type MOSFET, wherein an inverted channel region is formed in the boundary area of the base region to the trench by controlling an applied voltage to a gate electrode, such that current flows between the source electrode and the drain electrode through the source region and the drift region.

4 . A silicon carbide semiconductor device comprising:
a MOSFET including
a substrate of a first or second conductivity type comprising silicon carbide,
a drift layer of a first conductivity type comprising silicon carbide, the drift layer being disposed on the substrate and having an impurity concentration lower than the impurity concentration of the substrate,
a base region of a second conductivity type comprising silicon carbide, the base region being disposed on the drift layer in a cell region,
a source region of a first conductivity type comprising silicon carbide, the source region being disposed on the base region and having an impurity concentration higher than the impurity concentration of the drift layer,
a plurality of trenches, each of the trenches extending in a longitudinal direction and being deeper than the source region and the base region to reach the drift layer, the source region and the base region being disposed on both sides of the trenches,
a deep layer of a second conductivity type, the deep layer being disposed in surface portions of the drift layer under the base region between two adjacent trenches, the bottoms of the deep layer being disposed below the bottom of each of the trenches,
a gate insulating film disposed on the surface of each of the trenches,
a gate electrode disposed on the gate insulating film in each of the trenches,
an interlayer insulating film covering the gate electrode and the gate insulating film, the interlayer insulating film having a contact hole,
a source electrode electrically connected to the source region and the base region through the contact hole, and
a drain electrode disposed on the back side of the substrate; and
a peripheral high-breakdown-voltage structure including second-conductivity-type impurity layers surrounding the cell region, the second-conductivity-type impurity layers being at the bottom of a recessed mesa structure disposed on a peripheral region surrounding the cell region, the mesa structure being deeper than the source region and the base region to reach the drift layer, wherein the source region has a first recess, each of the trenches extends from the bottom of the first recess, the gate insulating film has an extension following the shape of the first recess, and the top surface of the gate electrode is flush with or below the top surface of the extension of the gate insulating film.

5 . The silicon carbide semiconductor device according to claim 4 wherein a cap oxide film is formed by oxidation of the top surface of the gate electrode, and the top surface of the cap oxide film of the gate electrode is flush with or below the top surface of the extension of the gate insulating film.

6 . The silicon carbide semiconductor device according to claim 4 wherein the MOSFET is an inverted-type MOSFET, wherein an inverted channel region is formed in the boundary area of the base region to the trench by controlling an applied voltage to a gate electrode, such that current flows between the source electrode and the drain electrode through the source region and the drift region.

7 . A method for manufacturing a silicon carbide semiconductor device comprising:
(a) forming a drift layer of a first conductivity type comprising silicon carbide on a substrate of a first or second conductivity type comprising of silicon carbide, the drift layer having an impurity concentration lower than the impurity concentration of the substrate; (b) forming a deep layer of a second conductivity type on a surface portion of the drift layer in a cell region and second-conductivity-type impurity layers surrounding the cell region in a peripheral region surrounding the cell region; (c) forming a base region of a second conductivity type comprising silicon carbide on the deep layer, the second-conductivity-type impurity layers, and the drift layer; (d) forming a first recess in the base region, forming a first-conductivity-type impurity layer comprising silicon carbide on the base region and the first recess, and then removing the first-conductivity-type impurity layer other than the portion on the first recess so as to leave a source region on the first recess and a second recess on the surface of the source region, the first-conductivity-type impurity layer having an impurity concentration higher than that of the drift layer; (e) forming a trench extending from the bottom surface of the second recess in the source region through the base region to the drift layer and having a longitudinal direction along an extension direction of the deep layer such that the trench is shallower than the deep layer, and at the same time, forming a recessed mesa structure by removing the base region in the peripheral region to expose the drift layer such that a peripheral high-b

Assignees

• Toyota Motor Co Ltd

Inventors

• Matsuki Hideo
• Sakakibara Jun
• Aoi Sachiko
• Watanabe Yukihiko
• Onogi Atsushi

Classifications

• H10D30/0297

  using recessing of the gate electrodes, e.g. to form trench gate electrodes · CPC title

• H10D12/038

  having a recessed gate, e.g. trench-gate IGBTs · CPC title

• H10D62/155

  Shapes  (cell layout of DMOS H10D62/127) · CPC title

• H10D62/109

  Reduced surface field [RESURF] PN junction structures · CPC title

• H10D62/8325

  Silicon carbide · CPC title