Semiconductor Device Structure for Improved Performance and Related Method

Patent metadata

Field	Value
Publication number	US-2017222002-A1
Application number	US-201615015021-A
Country	US
Kind code	A1
Filing date	Feb 3, 2016
Priority date	Feb 3, 2016
Publication date	Aug 3, 2017
Grant date	—

Abstract

A semiconductor device includes a vertical gate electrode in a gate trench in a semiconductor substrate, and a lateral gate electrode over the semiconductor substrate and adjacent the gate trench, where the lateral gate electrode results in improved electrical performance of the semiconductor device. The improved electrical performance includes an improved avalanche current tolerance in the semiconductor device. The improved electrical performance includes a reduced impact ionization under the gate trench. The improved electrical performance includes a reduced electric field under the gate trench. The lateral gate electrode results in an improved thermal stability in the semiconductor device.

First claim

1 . A semiconductor device comprising:
a drift region of a first conductivity type formed in a semiconductor substrate; a base region of a second conductivity type opposite said first conductivity type formed in said semiconductor substrate above said drift region; a first vertical gate structure extending through said base region into said drift region; a second vertical gate structure extending through said base region into said drift region; a first lateral gate structure over said semiconductor substrate between said first vertical gate structure and said second vertical gate structure; a second lateral gate structure over said semiconductor substrate between said first lateral gate structure and said second vertical gate structure; a source contact over said semiconductor substrate and contacting said base region or a body contact region in said base region between said first lateral gate structure and said second lateral gate structure; a first source region of said first conductivity type formed in said base region and extending uninterrupted from a sidewall of said first vertical gate structure to under said first lateral gate structure; a second source region of said first conductivity type formed in said base region and extending uninterrupted from under said first lateral gate structure to said source contact; a third source region of said first conductivity type formed in said base region and extending uninterrupted from said source contact to under said second lateral gate structure; and a fourth source region of said first conductivity type formed in said base region and extending uninterrupted from under said second lateral gate structure to a sidewall of said second vertical gate structure.

2 - 5 . (canceled)

6 . The semiconductor device of claim 1 , wherein said semiconductor device comprises a MOSFET.

7 . A semiconductor device, comprising:
a vertical gate electrode in a gate trench; a lateral gate electrode adjacent said gate trench; wherein said vertical gate electrode and said lateral gate electrode are configured to form a continuous current path which runs without interruption along a sidewall of said gate trench and under said lateral gate electrode.

8 - 11 . (canceled)

12 . The semiconductor device of claim 7 , wherein said semiconductor device comprises a MOSFET.

13 . A method of forming a semiconductor device, said method comprising:
forming a first vertical gate electrode in a first gate trench in a semiconductor substrate; forming a first lateral gate electrode over said semiconductor substrate and adjacent said first gate trench; and forming a first source region in said semiconductor substrate which extends uninterrupted from a sidewall of said first gate trench to under said first lateral gate electrode.

14 . (canceled)

15 . The method of claim 13 , further comprising forming a dielectric liner in said first gate trench.

16 . The method of claim 13 , wherein said first gate trench extends through a base region into a drift region of said semiconductor substrate.

17 . The method of claim 13 , further comprising forming a drift region over a drain region in said semiconductor substrate.

18 . The method of claim 13 , further comprising forming a conformal dielectric layer over said first vertical gate electrode and said first lateral gate electrode.

19 . The method of claim 13 , further comprising forming a gate dielectric cap over said first vertical gate electrode and said first lateral gate electrode.

20 . The method of claim 13 , further comprising:
forming a second source region in said semiconductor substrate, said second source region being spaced apart from said first source region and extending uninterrupted from under said first lateral gate electrode to a contact trench in said semiconductor substrate; and forming a source contact in said contact trench, said source contact being coupled to said second source region.

21 . The method of claim 13 , further comprising:
forming a second vertical gate electrode in a second gate trench in said semiconductor substrate; forming a second lateral gate electrode over said semiconductor substrate and adjacent said second gate trench; forming a second source region in said semiconductor substrate which extends uninterrupted from a sidewall of said second gate trench to under said second lateral gate electrode; and forming a source contact between said first lateral gate electrode and said second lateral gate electrode.

Assignees

• Infineon Technologies Americas Corp

Inventors

• Chen Jingjing

Classifications

• H10P14/40

  of conductive or resistive materials · CPC title

• H01L29/41725

  Electricity · mapped topic

• H01L29/0882

  Electricity · mapped topic

• H01L29/0865

  Electricity · mapped topic

• H01L29/7813

  Electricity · mapped topic