Approach to fabrication of an on-chip resistor with a field effect transistor

Patent metadata

Field	Value
Publication number	US-9917082-B1
Application number	US-201715407592-A
Country	US
Kind code	B1
Filing date	Jan 17, 2017
Priority date	Jan 17, 2017
Publication date	Mar 13, 2018
Grant date	Mar 13, 2018

Abstract

A method of forming a resistor adjacent to a fin field effect transistor on a substrate, including, forming a plurality of vertical fins on the substrate, forming a dielectric fill layer on the plurality of vertical fins, forming at least two dummy gate structures on the plurality of vertical fins, forming a replaceable resistor structure on the dielectric fill layer over a region of the substrate unoccupied by vertical fins, forming a sidewall spacer on the at least two dummy gate structures and the replaceable resistor structure, removing the replaceable resistor structure to form a trench, and forming a resistor structure in the trench.

First claim

What is claimed is:

1. A method of forming a resistor adjacent to a fin field effect transistor on a substrate, comprising:
forming a plurality of vertical fins on the substrate;
forming a dielectric till layer on the plurality of vertical fins;
forming at least two dummy gate structures on the plurality of vertical fins;
forming a replaceable resistor structure on the dielectric fill layer over a region of the substrate unoccupied by vertical fins;
forming a sidewall spacer on the at least two dummy gate structures and the replaceable resistor structure;
removing the replaceable resistor structure to form a trench; and
forming a resistor structure in the trench.

2. The method of claim 1 , wherein the sidewall spacer is silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon boronitride (SiBN), silicon borocarbide (SiBC), silicon boro carbonitride (SiBCN), boron carbide (BC), boron nitride (BN), or combinations thereof.

3. The method of claim 2 , wherein the resistor structure is at least partially formed on the dielectric fill layer.

4. The method of claim 3 , wherein the resistor structure is formed by forming a pinch-off layer on the sidewall spacer, a resistor layer on the pinch-off layer, and an insulating fill layer on the resistor layer.

5. The method of claim 4 , where the resistor layer is tungsten silicide (WSi), tungsten (W), titanium nitride (TiN), or combinations thereof.

6. The method of claim 1 , further comprising removing at least a portion of one of the at least two dummy gate structures to form a dummy gate trench.

7. The method of claim 6 , further comprising filling the dummy gate trench with the pinch-off layer, where the thickness of the pinch-off layer is based on the width of the dummy gate trench to be filled.

8. The method of claim 1 , wherein the plurality of vertical fins are formed by a sidewall image transfer process.

9. A method of forming an arrangement of 3 -dimensional resistors and tin field effect transistors on a region of a substrate, comprising:
forming a plurality of vertical fins on the substrate;
forming a dielectric fill layer on the plurality of vertical fins;
forming at least two dummy gate ctures across the plurality of vertical fins;
forming at least one replaceable resistor structure on the dielectric fill layer, where the at least one replaceable resistor structure is adjacent to the end faces of the plurality of vertical fins;
forming a sidewall spacer on each of the at least two dummy gate structures and the at least one replaceable resistor structure;
forming an interlayer dielectric (ILD) layer on the sidewall spacer on each of the at least two dummy gate structures and the at least one replaceable resistor structure, where the ILD layer fills in spaces between the sidewall spacers;
removing the at least one replaceable resistor structure to form a resistor trench and expose the sidewall spacer;
forming a pinch-off layer on the exposed sidewall spacer;
forming a resistor layer on the pinch-off layer; and
forming an insulating fill layer on the resistor layer.

10. The method of claim 9 , wherein the resistor layer is tungsten silicide (WSi), tungsten (W), titanium nitride (TiN), or combinations thereof.

11. The method of claim 9 , wherein the resistor layerhas a thickness in the range of about 5 nm to about 30 nm.

12. The method of claim 9 , further comprising removing at least a portion of one of the at least two dummy gate structures to form a dummy gate trench, wherein the pinch-off layer fills the dummy gate trench.

13. The method of claim 12 , wherein the pinch-off layer has a thickness in the range of about 5 nm to about 20 nm, and the dummy gate trench has a width of twice the pinch-off layer thickness or less.

14. The method of claim 9 , further comprising removing the at least two dummy gate structures, and forming a gate structure by forming a gate dielectric layer on at least a portion of at least one of the vertical fins, forming a work function layer on at least a portion of the gate dielectric layer, and forming a gate till layer on at least a portion of the work function layer.

Assignees

• IBM

Inventors

• Basker Veeraraghavan S
• Cheng Kangguo
• Standaert Theodorus E
• Wang Junli

Classifications

• H01L27/0629 Primary

  Electricity · mapped topic

• H01L21/823431

  Electricity · mapped topic

• H01L28/24

  Electricity · mapped topic

• H01L21/823437

  Electricity · mapped topic

• H01L29/66545

  Electricity · mapped topic