Detection of data corruption in memory address decode circuitry

Patent metadata

Field	Value
Publication number	US-12417042-B2
Application number	US-202117540847-A
Country	US
Kind code	B2
Filing date	Dec 2, 2021
Priority date	Dec 2, 2021
Publication date	Sep 16, 2025
Grant date	Sep 16, 2025

Abstract

A memory controller including memory address decode circuitry that detects silent data errors that occur in the memory address decode circuitry during runtime is provided. The memory address decode circuitry includes address decode circuitry to covert a received physical address to a memory address, reverse address decode circuitry to convert the memory address to a second physical address and address compare circuitry to compare the received physical address and the second physical address to detect a silent error.

First claim

What is claimed is:

1. A memory controller comprising:
memory address decode circuitry, the memory address decode circuitry including:
address decode circuitry to convert a received physical address to a memory address;
reverse address decode circuitry to receive the memory address from the address decode circuitry and to convert the memory address to a second physical address; and
address compare circuitry to compare the received physical address and the second physical address, the received physical address to be forwarded to a scheduler in the memory controller for use by a memory if the received physical address and the second physical address match.

2. The memory controller of claim 1 , wherein if the received physical address and the second physical address do not match, the memory controller to block a transaction to use the received physical address and to flag an error.

3. The memory controller of claim 1 , if the received physical address and the second physical address are not the same, the memory controller to replay a transaction using the received physical address.

4. The memory controller of claim 1 , wherein the memory controller to detect silent data errors that occur in the address decode circuitry or reverse address decode circuitry during runtime.

5. The memory controller of claim 1 , wherein the memory is a volatile memory.

6. The memory controller of claim 5 , wherein the volatile memory is a Dynamic Random Access Memory.

7. The memory controller of claim 6 , wherein the memory address includes a row address, a column address and a bank address.

8. A method performed by a memory controller comprising:
converting, in address decode circuitry, a received physical address to a memory address;
converting, in reverse address decode circuitry, the memory address to a second physical address;
comparing, in address compare circuitry, the received physical address and the second physical address; and
forwarding the received physical address to a scheduler in the memory controller for use by a memory if the received physical address and the second physical address match.

9. The method of claim 8 , wherein if the received physical address and the second physical address do not match, the memory controller to block a transaction to use the received physical address and to flag an error.

10. The method of claim 8 , if the received physical address and the second physical address are not the same, the memory controller to replay a transaction using the received physical address.

11. The method of claim 8 , wherein the memory controller to detect silent data errors that occur in the address decode circuitry or reverse address decode circuitry during runtime.

12. The method of claim 8 , wherein the memory is a Dynamic Random Access Memory.

13. The method of claim 12 , wherein the memory address includes a row address, a column address and a bank address.

14. A system comprising:
a processor, and
a memory controller communicatively coupled to the processor, the memory controller comprising:
memory address decode circuitry, the memory address decode circuitry including:
address decode circuitry to convert a received physical address to a memory address;
reverse address decode circuitry to receive the memory address from the address decode circuitry and to convert the memory address to a second physical address; and
address compare circuitry to compare the received physical address and the second physical address, the received physical address to be forwarded to a scheduler in the memory controller for use by a memory if the received physical address and the second physical address match.

15. The system of claim 14 , wherein if the received physical address and the second physical address do not match, the memory controller to block a transaction to use the received physical address and to flag an error.

16. The system of claim 14 , if the received physical address and the second physical address are not the same, the memory controller to replay a transaction using the received physical address.

17. The system of claim 14 , wherein the memory controller to detect silent data errors that occur in the address decode circuitry or reverse address decode circuitry during runtime.

18. The system of claim 14 , wherein the memory is a Dynamic Random Access Memory.

19. The system of claim 18 , wherein the memory address includes a row address, a column address and a bank address.

20. The system of claim 14 , further comprising one or more of:
a display communicatively coupled to the processor; or
a battery coupled to the processor.

Assignees

• Intel Corp

Inventors

• Mandava Sreenivas
• Ling Jing

Classifications

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F11/1474

  in transactions (updating of structured data in databases G06F16/23) · CPC title

• G06F11/0763

  by bit configuration check, e.g. of formats or tags · CPC title

• G06F3/0638 Primary

  Organizing or formatting or addressing of data · CPC title