Memory transaction queue bypass based on configurable address and bandwidth conditions
US-12541460-B2 · Feb 3, 2026 · US
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Ling Jing patents
Ling Jing is listed as an inventor on 25 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Ling Jing |
| Total patents | 25 |
| First publication | Aug 18, 2015 |
| Latest publication | Feb 3, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Hardware traffic generator using linear feedback shift registers for testing of memory subsystems
US-2026029964-A1 · Jan 29, 2026 · US
Methods and apparatus to manage memory movement
US-2025321676-A1 · Oct 16, 2025 · US
Detection of data corruption in memory address decode circuitry
US-12417042-B2 · Sep 16, 2025 · US
Fast memory ECC error correction
US-12242342-B2 · Mar 4, 2025 · US
Adaptive error correction to improve system memory reliability, availability, and serviceability (RAS)
US-12235720-B2 · Feb 25, 2025 · US
Apparatus and method to reduce memory power consumption in a memory phy in a memory controller
US-2024193109-A1 · Jun 13, 2024 · US
Adaptive error correction to improve system memory reliability, availability, and serviceability (ras)
US-2024061741-A1 · Feb 22, 2024 · US
Memory transaction queue bypass based on configurable address and bandwidth conditions
US-2022179797-A1 · Jun 9, 2022 · US
Fast memory ecc error correction
US-2022107866-A1 · Apr 7, 2022 · US
Recent patents
Latest publications not already listed above.
Address generation for adaptive double device data correction sparing
US-2022108764-A1 · Apr 7, 2022 · US
Detection of data corruption in memory address decode circuitry
US-2022091764-A1 · Mar 24, 2022 · US
Apparatus, system, and method to flush modified data from a volatile memory to a persistent second memory
US-11036634-B2 · Jun 15, 2021 · US
Boot process with parallel memory initialization
US-10346177-B2 · Jul 9, 2019 · US
Apparatus, system, and method to flush modified data from a volatile memory to a persistent second memory
US-2019171568-A1 · Jun 6, 2019 · US
Apparatus, system, and method to flush modified data from a volatile memory to a persistent second memory
US-10198354-B2 · Feb 5, 2019 · US
Apparatus and method for generating local binary patterns (LBPS)
US-10129495-B2 · Nov 13, 2018 · US
Apparatus, system, and method to flush modified data from a volatile memory to a persistent second memory
US-2018276124-A1 · Sep 27, 2018 · US
Boot Process with Parallel Memory Initialization
US-2018165100-A1 · Jun 14, 2018 · US
Apparatus and method for generating local binary patterns (lbps)
US-2017280079-A1 · Sep 28, 2017 · US
Dynamically changing lockstep configuration
US-9697094-B2 · Jul 4, 2017 · US
Differential delay compensation
US-9430378-B2 · Aug 30, 2016 · US
Dynamically changing lockstep configuration
US-2016232063-A1 · Aug 11, 2016 · US
Differential delay compensation
US-2015350114-A1 · Dec 3, 2015 · US
Differential delay compensation
US-9110794-B2 · Aug 18, 2015 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 20 |
| Micron Technology Inc | 3 |
| Qualcomm Inc | 2 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F11/1048 | 5 |
| G11C29/42 | 5 |
| G06F12/0866 | 4 |
| G06F2212/621 | 4 |
| G06F12/12 | 4 |