Dynamically changing lockstep configuration

Patent metadata

Field	Value
Publication number	US-9697094-B2
Application number	US-201514672131-A
Country	US
Kind code	B2
Filing date	Mar 28, 2015
Priority date	Feb 6, 2015
Publication date	Jul 4, 2017
Grant date	Jul 4, 2017

Abstract

Memory subsystem error management enables dynamically changing lockstep partnerships. A memory subsystem has a lockstep partnership relationship between a first memory portion and a second memory portion to spread error correction over the pair of memory resources. The lockstep partnership can be preconfigured. In response to detecting a hard error in the lockstep partnership, the memory subsystem can cancel or reverse the lockstep partnership between the first memory portion and the second memory portion and create or set a new lockstep partnership. The detected error can be a second hard error in the lockstep partnership. The memory subsystem can create new lockstep partnerships between the first memory portion and a third memory portion as lockstep partners and between the second memory portion and a fourth memory portion as lockstep partners. The memory subsystem can also be configured to change the granularity of the lockstep partnership when changing partnerships.

First claim

What is claimed is:

1. A method for managing errors in a memory subsystem, comprising:
detecting a hard error in a first memory portion set in a lockstep partnership as a lockstep partner with a second memory portion, wherein error correction is to be spread over the lockstep partners;
responsive to detecting the hard error, canceling the lockstep partnership between the first memory portion and the second memory portion;
creating a new lockstep partnership between the first memory portion and a third memory portion as lockstep partners; and
creating a new lockstep partnership between the second memory portion and a fourth memory portion as lockstep partners.

2. The method of claim 1 , wherein detecting the hard error comprises detecting a second hard error in the lockstep partnership.

3. The method of claim 1 , wherein the lockstep partnership comprises a virtual lockstep partnership where the hard error is mapped out to a spare memory portion.

4. The method of claim 1 , wherein the first and second memory portions comprise ranks of memory.

5. The method of claim 1 , wherein the first and second memory portions comprise banks of memory.

6. The method of claim 1 , wherein the first and second memory portions comprise DRAM (dynamic random access memory) devices.

7. The method of claim 6 , wherein the first and second memory portions comprise DRAM devices in separate ranks.

8. The method of claim 6 , wherein the third and fourth memory portions comprise DRAM devices in different ranks.

9. The method of claim 1 , wherein at least one of creating the new lockstep partnership between the first memory portion and a third memory portion as lockstep partners or creating the new lockstep partnership between the second memory portion and a fourth memory portion as lockstep partners includes changing a level of granularity of the lockstep partnership.

10. The method of claim 9 , wherein detecting the hard error in the first memory portion comprises detecting a hard error in a memory portion that can be grouped with the first memory portion at a different level of granularity, and wherein creating the new lockstep partnership comprises creating a new lockstep partnership between the first memory portion and the third memory portion at the different level of granularity.

11. The method of claim 1 , wherein creating the new lockstep partnerships comprises dynamically changing a lockstep partnership entry in a lockstep table.

12. A memory management device to manage errors in an associated memory subsystem, comprising:
a hardware interface to couple with multiple memory portions over a bus;
processor circuitry to execute error detection logic to detect a hard error in a first memory portion of the memory subsystem, wherein the first memory portion is set in a lockstep partnership as a lockstep partner with a second memory portion, wherein error correction is to be spread over the lockstep partners; and
processor circuitry to execute error correction logic to cancel the lockstep partnership between the first and second memory portions responsive to detecting the hard error in the first memory portion, and to create a new lockstep partnerships between the first memory portion and a third memory portion as lockstep partners and between the second memory portion and a fourth memory portion as lockstep partners.

13. The memory management device of claim 12 , wherein the lockstep partnership comprises a virtual lockstep partnership where the hard error is mapped out to a spare memory portion.

14. The memory management device of claim 12 , wherein the first and second memory portions comprise one of ranks of memory, banks of memory, or DRAM (dynamic random access memory) devices.

15. The memory management device of claim 14 , wherein the first and second memory portions comprise DRAM devices in separate ranks.

16. The memory management device of claim 14 , wherein the third and fourth memory portions comprise DRAM devices in different ranks.

17. The memory management device of claim 12 , wherein the error correction logic is to change a level of granularity of at least one lockstep partnership when creating the new lockstep partnership between the first memory portion and a third memory portion as lockstep partners, or the new lockstep partnership between the second memory portion and a fourth memory portion as lockstep partners.

18. The memory management device of claim 17 , wherein the error detection logic is to detect the hard error in a memory portion that can be grouped with the first memory portion at a different level of granularity, and wherein the error correction logic is to create the new lockstep partnership between the first memory portion and the third memory portion at the different level of granularity.

19. An electronic device with a memory subsystem, comprising:
multiple DRAMs (dynamic random access memory devices) each including a memory array, wherein the memory arrays are addressable according to multiple different levels of granularity;
a memory controller to control access to the DRAM, the memory controller including
error detection logic to detect a hard error in a first memory portion of the memory subsystem, wherein the first memory portion is set in a lockstep partnership as a lockstep partner with a second memory portion, wherein error correction is to be spread over the lockstep partners; and
error correction logic to cancel the lockstep partnership between the first and second memory portions responsive to detecting the hard error in the first memory portion, and to create a new lockstep partnerships between the first memory portion and a third memory portion as lockstep partners and between the second memory portion and a fourth memory portion as lockstep partners; and

a chassis system to couple the memory system to a blade server.

20. The electronic device of claim 19 , wherein the lockstep partnership comprises a virtual lockstep partnership where the hard error is mapped out to a spare memory portion.

21. The electronic device of claim 19 , wherein the first and second memory portions comprise one of ranks of memory, banks of memory, or DRAM (dynamic random access memory) devices.

22. The electronic device of claim 19 , wherein the error correction logic is to change a level of granularity of at least one lockstep partnership when creating the new lockstep partnership between the first memory portion and a third memory portion as lockstep partners, or the new lockstep partnership between the second memory portion and a fourth memory portion as lockstep partners.

Assignees

• Intel Corp

Inventors

• Das Debaleena
• Huang George H
• Ling Jing
• Daftari Reza E
• Ganesan Meera

Classifications

• G06F2201/825

  the problem or solution involving locking · CPC title

• G06F3/0644

  Management of space entities, e.g. partitions, extents, pools · CPC title

• G06F3/0683

  Plurality of storage devices · CPC title

• G06F11/20

  using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements · CPC title

• G06F11/108

  Parity data distribution in semiconductor storages, e.g. in SSD · CPC title