Mapping a physical address differently to different memory devices in a group

Patent metadata

Field	Value
Publication number	US-9934143-B2
Application number	US-201314038659-A
Country	US
Kind code	B2
Filing date	Sep 26, 2013
Priority date	Sep 26, 2013
Publication date	Apr 3, 2018
Grant date	Apr 3, 2018

Abstract

A memory subsystem includes a group of memory devices connected to an address bus. The memory subsystem includes logic to uniquely map a physical address of a memory access command to each memory device of the group. Thus, each physical address sent by an associated memory controller uniquely accesses a different row of each memory device, instead of being mapped to the same or corresponding row of each memory device.

First claim

What is claimed is:

1. A memory subsystem comprising:
a common address bus to provide a physical address from an associated memory controller; and
multiple memory devices within a same rank of a dual inline memory module coupled to the common address bus, each memory device including:
a memory array having multiple rows of memory, each row having a physical location uniquely addressable within the memory array; and
interface elements to couple to the common address bus to receive the physical address provided by the associated memory controller, the same physical address to uniquely map to rows at different active physical locations within the respective memory arrays of the memory devices such that no memory device within the rank has a same physical address to row mapping as any other memory device within the rank and such that each of the different active physical locations are concurrently accessed as the physical address's target in response to each memory device receiving the physical address, wherein, the interface elements collectively implement the unique physical address to row mapping for core accesses of the memory devices but not for mode register accesses of the memory devices.

2. The memory subsystem of claim 1 , wherein the multiple memory devices comprise dual data rate dynamic random access memory devices.

3. The memory subsystem of claim 1 , wherein the multiple memory devices comprise a memory device group.

4. The memory subsystem of claim 1 , wherein the multiple memory devices coupled to the common address bus includes a number of memory devices that exceeds a capacity of bits in the physical address to uniquely map to rows at different locations of each respective memory device, and further comprising the physical address and an additional address signal line to uniquely map to rows at different physical locations within the respective memory arrays of each respective memory device.

5. The memory subsystem of claim 4 , wherein the additional address signal line comprises a bank address signal line.

6. The memory subsystem of claim 4 , wherein the additional address signal line comprises an address inversion signal line.

7. The memory subsystem of claim 1 , wherein the common address bus further comprises a number of signal lines, one for each bit of the physical address, where each signal line of the common address bus is mapped to different corresponding address connectors of each respective memory device.

8. The memory subsystem of claim 7 , wherein each signal line is mapped to a corresponding address connector of a first memory device, and mapped to successively offset address connectors of subsequent memory devices.

9. The memory subsystem of claim 1 , wherein each memory device further comprises address mapping logic to map bits of the physical address to different rows within respective memory devices, wherein the address mapping logic of the multiple memory devices each is to implement a different mapping pattern from address mapping logic of other memory devices.

10. The memory subsystem of claim 9 , wherein each address mapping logic is to implement a different hash function to map the physical address.

11. The memory subsystem of claim 9 , wherein each memory device has its mapping pattern registered with a BIOS (basic input/output system) of a computing device of which the memory subsystem is a part.

12. The memory subsystem of claim 9 , wherein each memory device is to hash row address bits for access to the memory array, but does not hash address bits for access to a Mode Register.

13. An electronic device comprising:
a host hardware platform including a processor;
a memory subsystem including
a common address bus to provide a physical address from an associated memory controller; and
multiple memory devices within a same rank of a dual-in line module coupled to the common address bus, each memory device including
a memory array having multiple rows of memory, each row having a physical location uniquely addressable within the memory array; and
interface elements to couple to the common address bus to receive the physical address provided by the associated memory controller, the same physical address to uniquely map to rows at different active physical locations within the respective memory arrays of the memory devices such that no memory device within the rank has a same physical address to row mapping as any other memory device within the rank and such that each of the different active physical locations are concurrently accessed as the physical address's target in response to each memory device receiving the physical address, wherein, the interface elements collectively implement the unique physical address to row mapping for core accesses of the memory devices but not for mode register accesses of the memory devices; and
a touchscreen display coupled to generate a display based on data accessed from the memory device.

14. The electronic device of claim 13 , wherein the common address bus further comprises a number of signal lines, one for each bit of the physical address, where each signal line of the common address bus is mapped to different corresponding address connectors of each respective memory device.

15. The electronic device of claim 13 , wherein each memory device further comprises address mapping logic to map bits of the physical address to different rows within respective memory devices, wherein the address mapping logic of the multiple memory devices each is to implement a different mapping pattern from address mapping logic of other memory devices.

16. A method, comprising:
receiving a core memory access command from a memory controller, the core memory access command including a physical address for the core memory access command, the core memory access command received on a common address bus to which multiple memory devices within a same rank of a dual-in line module are coupled, wherein each memory device includes rows of memory with uniquely addressable physical locations within the memory device;
mapping the physical address from interface elements of the multiple memory devices to rows of the multiple memory devices, including uniquely mapping the physical address to different active physical locations within each of the multiple memory devices such that no memory device within the rank has a same physical address to row mapping as any other memory device within the rank and such that each of the different active physical locations are concurrently accessed as the physical address's target in response to each memory device receiving the physical address; and
receiving a mode register access command from the memory controller and refraining from uniquely mapping the mode register's physical address to different active physical locations within the multiple memory devices.

17. The method of claim 16 , wherein the multiple memory devices coupled to the common address bus includes a number of memory devices that exceeds a capacity of row address bits in the physical address to uniquely map to rows at different locations of each respective memory device, and wherein mapping the physical address further comprises uniquely mapping the physical address based on both row address bits as well as an additional address signal bit.

18. The method of claim 16 , wherein the common address bus includes a number of signal lines, one for each bit of the physical address, and wherein mapping the physical address from the interface elements to the multiple memory devices comprises uniquely mapping the signal lines

Assignees

• Intel Corp

Inventors

• Bains Kuljit S
• Sah Suneeta
• Crawford John H
• Morris Brian S

Classifications

• G06F12/0638

  Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module (address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70) · CPC title

• G06F12/0292

  using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10) · CPC title

• G06F12/06 Primary

  Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication (G06F12/08 takes precedence) · CPC title