Semiconductor device and data storage system including the same

Patent metadata

Field	Value
Publication number	US-12414301-B2
Application number	US-202217961070-A
Country	US
Kind code	B2
Filing date	Oct 6, 2022
Priority date	Dec 30, 2021
Publication date	Sep 9, 2025
Grant date	Sep 9, 2025

Abstract

A semiconductor device includes a contact plug forming a signal path electrically connecting a bitline or wordlines and an upper connection pattern to each other, a lower insulating structure includes first and second insulating portions; the contact plug penetrates through the second insulating portion and contacts the upper connection pattern; the first insulating portion includes first and second lower layers, the second lower layer having a thickness smaller than the first lower layer; the second insulating portion includes a first upper layer contacting the second lower layer and covering a portion of an upper surface of the upper connection pattern, and a second upper layer on the first upper layer, the second upper layer having a thickness greater than the first upper layer; and materials of the second lower layer and first upper layer is different from materials of the first lower layer and the second upper layer.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a lower structure including a semiconductor substrate, a circuit device on the semiconductor substrate, a circuit interconnection structure including connection patterns electrically connected to the circuit device and at different height levels, and a lower insulating structure covering the circuit device and the circuit interconnection structure on the semiconductor substrate;
an upper structure on the lower structure and including wordlines stacked and spaced apart from each other in a vertical direction, a vertical memory structure penetrating through the wordlines, and a bitline electrically connected to the vertical memory structure on the vertical memory structure; and
a contact plug forming at least a portion of a signal path electrically connecting at least one of the bitline and the wordlines and at least one of the connection patterns to each other, wherein:
the connection patterns include an upper connection pattern contacting the contact plug;
the lower insulating structure includes a first insulating portion on a side surface of the upper connection pattern and a second insulating portion on the first insulating portion and on the upper connection pattern;
the contact plug penetrates through the second insulating portion and contacts the upper connection pattern;
the first insulating portion includes a first lower layer and a second lower layer on the first lower layer, the second lower layer having a thickness smaller than a thickness of the first lower layer;
the second insulating portion includes:
a first upper layer contacting the second lower layer and covering at least a portion of an upper surface of the upper connection pattern, and
a second upper layer on the first upper layer, the second upper layer having a thickness greater than a thickness of the first upper layer; and

a material of the second lower layer and the first upper layer is different from a material of the first lower layer and the second upper layer.

2. The semiconductor device as claimed in claim 1 , wherein the thickness of the first upper layer is different from the thickness of the second lower layer.

3. The semiconductor device as claimed in claim 1 , wherein the thickness of the first upper layer is smaller than the thickness of the second lower layer.

4. The semiconductor device as claimed in claim 1 , wherein:
the thickness of the second lower layer is in a range of about 400 angstroms to about 600 angstroms; and
the thickness of the first upper layer is in a range of about 285 angstroms to about 315 angstroms.

5. The semiconductor device as claimed in claim 1 , wherein:
the material of the first lower layer and the second upper layer is a silicon oxide; and
the material of the second lower layer and the first upper layer is a silicon nitride.

6. The semiconductor device as claimed in claim 1 , wherein the first upper layer contacts at least the portion of the upper surface of the upper connection pattern.

7. The semiconductor device as claimed in claim 1 , further comprising:
a buffer layer between the first upper layer and the upper connection pattern,
wherein the buffer layer contacts the first upper layer and the upper connection pattern.

8. The semiconductor device as claimed in claim 7 , wherein the buffer layer includes an oxide of a material of the upper connection pattern.

9. The semiconductor device as claimed in claim 1 , wherein:
the first lower layer includes a silicon oxide;
the second lower layer includes a silicon oxynitride formed by nitriding a silicon oxide using a plasma nitridation process; and
the first upper layer includes a silicon nitride formed by a deposition process.

10. The semiconductor device as claimed in claim 9 , wherein:
an upper region of the upper connection pattern includes a region nitrided by the plasma nitridation process; and
the contact plug penetrates through the nitrided region of the upper connection pattern and contacts the upper connection pattern.

11. The semiconductor device as claimed in claim 1 , wherein the upper connection pattern has a convex upper surface.

12. The semiconductor device as claimed in claim 1 , wherein the upper connection pattern has a concave upper surface.

13. The semiconductor device as claimed in claim 1 , wherein:
the contact plug includes:
a first portion penetrating through the second upper layer;
a second portion penetrating through the first upper layer; and
a third portion extending inwardly in the upper connection pattern and contacting the upper connection pattern; and

a minimum width of the second portion is smaller than a maximum width of the first portion.

14. The semiconductor device as claimed in claim 1 , wherein:
the upper structure further includes a pattern structure including a silicon layer;
the vertical memory structure includes an insulating core region, a channel layer covering at least a side surface of the insulating core region, and a data storage structure covering at least an external side surface of the channel layer;
the data storage structure includes a first dielectric layer, a second dielectric layer, and a data storage layer between the first and second dielectric layers; and
the channel layer contacts the silicon layer.

15. The semiconductor device as claimed in claim 14 , wherein:
the upper structure further includes insulating layers stacked and spaced apart from each other in the vertical direction;
at least some of the insulating layers are at a same height level as the wordlines; and
the contact plug penetrates through the insulating layers and extends downwardly to contact the upper connection pattern.

16. A semiconductor device, comprising:
a lower structure including a semiconductor substrate, a circuit device on the semiconductor substrate, a circuit interconnection structure including connection patterns electrically connected to the circuit device and at different height levels, and a lower insulating structure covering the circuit device and the circuit interconnection structure on the semiconductor substrate;
an upper structure on the lower structure and including wordlines stacked and spaced apart from each other in a vertical direction, a vertical memory structure penetrating through the wordlines, and a bitline electrically connected to the vertical memory structure on the vertical memory structure; and
a contact plug forming at least a portion of a signal path electrically connecting at least one of the bitline and the wordlines and at least one of the connection patterns to each other, wherein:
the connection patterns include an upper connection pattern contacting the contact plug;
the lower insulating structure includes a first insulating portion on a side surface of the upper connection pattern and a second insulating portion on the first insulating portion and on the upper connection pattern;
the contact plug penetrates through the second insulating portion and contacts the upper connection pattern;
the upper connection pattern includes a plug portion and a barrier layer covering a side surface and a bottom surface of the plug portion;
the upper connection pattern includes a groove between an upper end of the barrier layer and the plug portion, in an upper region of the upper connection pattern;
the second insulating portion includes:
a first upper layer contacting the first insulating portion and covering at least a portion of an upper surface of the upper connection pattern, and
a second upper layer on the first upper layer, the second upper layer

Assignees

• Samsung Electronics Co Ltd

Inventors

• Woo Youngbum
• Lim Joonsung
• Kim Junhyoung
• Lee Seungmin

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10W20/075

  of multilayered thin functional dielectric layers · CPC title

• H10W20/096

  by contacting with gases, liquids or plasmas · CPC title