Bonded three-dimensional memory devices and methods of making the same by replacing carrier substrate with source layer

Patent metadata

Field	Value
Publication number	US-11355486-B2
Application number	US-202017062988-A
Country	US
Kind code	B2
Filing date	Oct 5, 2020
Priority date	Feb 13, 2019
Publication date	Jun 7, 2022
Grant date	Jun 7, 2022

Abstract

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a carrier substrate. Memory stack structures vertically extend through the alternating stack. Each memory stack structure includes a respective vertical semiconductor channel and a respective memory film. The memory die can be bonded to a logic die containing peripheral circuitry for supporting operations of memory cells within the memory die. A distal end of each of the vertical semiconductor channels is physically exposed by removing the carrier substrate. A source layer is formed directly on the distal end each of the vertical semiconductor channels. A source power supply network can be formed on the backside of the source layer.

First claim

The invention claimed is:

1. A semiconductor structure comprising a memory die bonded to a logic die, the memory die comprising:
an alternating stack of insulating layers and electrically conductive layers;
memory openings extending through the alternating stack;
memory opening fill structures located in the memory openings and comprising a respective vertical semiconductor channel and a respective memory film;
a source layer having a front side electrically connected to first end portions of the vertical semiconductor channels that are distal from an interface between the logic die and the memory die;
an electrically conductive layer connected to a back side of the source layer; and
backside bonding pads electrically connected to the electrically conductive layer.

2. The semiconductor structure of claim 1 , wherein electrically conductive layer comprises a source power supply network.

3. The semiconductor structure of claim 2 , wherein the source power supply network comprises backside metal interconnect structures embedded in a backside isolation dielectric layer and contacting the source layer at multiple locations.

4. The semiconductor structure of claim 3 , wherein the source power supply network comprises:
a network of metal lines; and
metal via structures vertically extending between the network of metal lines and a backside surface of the source layer.

5. The semiconductor structure of claim 4 , wherein the network of metal lines comprises:
first metal lines laterally extending along a first horizontal direction; and
second metal lines laterally extending along a second horizontal direction and adjoined to a respective subset of the first metal lines to form a mesh.

6. The semiconductor structure of claim 3 , further comprising a passivation dielectric layer located on a backside of the backside isolation dielectric layer and embedding the network of metal lines.

7. The semiconductor structure of claim 6 , wherein:
the backside isolation dielectric layer contacts proximal planar surfaces of the network of metal lines; and
the passivation dielectric layer contacts sidewalls and distal planar surfaces of the network of metal lines.

8. The semiconductor structure of claim 6 , wherein the passivation dielectric layer comprises an array of openings therethrough within areas of the backside bonding pads.

9. The semiconductor structure of claim 3 , further comprising support pillar structures vertically extending through the alternating stack and comprising a respective dummy vertical semiconductor channel and a dummy memory film, wherein the support pillar structures contact the backside isolation dielectric layer and does not contact the source layer.

10. The semiconductor structure of claim 1 , wherein interfaces between the source layer and the vertical semiconductor channels comprise portions that are more distal from the interface between the logic die and the memory die than an interface between the source layer and the alternating stack is from the interface between the logic die and the memory die.

11. The semiconductor structure of claim 10 , wherein the interfaces between the source layer and the vertical semiconductor channels comprise cylindrical surfaces or tapered surfaces that are not parallel to the interface between the logic die and the memory die.

12. The semiconductor structure of claim 1 , further comprising a stepped dielectric material portion in contact with stepped surfaces of the alternating stack.

13. The semiconductor structure of claim 12 , further comprising;
a connection via structure vertically extending through the stepped dielectric material portion;
a contact via structure embedded within the backside isolation dielectric layer; and
an additional backside bonding pad electrically connected to the contact via structure.

14. A method of forming a semiconductor structure, comprising:
forming a memory die over a carrier substrate, wherein the memory die comprises an alternating stack of insulating layers and electrically conductive layers, and memory opening fill structures located in memory openings extending through the alternating stack and comprising a respective vertical semiconductor channel and a respective memory film;
detaching the carrier substrate from the memory die;
forming a source layer located on a backside surface of the alternating stack;
forming a backside isolation dielectric layer on a backside surface of the source layer;
forming a source power supply network including backside metal interconnect structures on the backside isolation dielectric layer, wherein the source power supply network comprises metal via structures extending through the backside isolation dielectric layer and contacting the source layer at multiple locations; and
forming backside bonding pads electrically connected to the source power supply network.

15. The method of claim 14 , wherein the source power supply network and the backside bonding pads are formed by:
forming via cavities vertically extending through the backside isolation dielectric layer;
depositing at least one metallic material in the via cavities and over a backside surface of the backside isolation dielectric layer; and
patterning the at least one metallic material, wherein patterned portions of the at least one metallic material comprise the source power supply network and the backside bonding pads.

16. The method of claim 14 , further comprising:
forming the alternating stack of the insulating layers and the electrically conductive layers and the memory opening fill structures over a semiconductor material layer;
removing the semiconductor material layer selective to the alternating stack and the memory opening fill structures;
removing physically exposed portions of the memory films; and
forming the source layer on physically exposed end portions of the vertical semiconductor channels.

17. The method of claim 14 , further comprising:
the memory die comprises first bonding structures electrically connected to the vertical semiconductor channels or the electrically conductive layers; and
the method further comprises:
providing a logic die comprising semiconductor devices and second bonding structures that are electrically connected to the semiconductor devices;
attaching the logic die to the memory die by bonding the second bonding structures to the first bonding structures while the carrier substrate is attached to the memory die; and
detaching the carrier substrate from the memory die after the logic die is attached to the memory die.

18. The method of claim 14 , wherein the source power supply network comprises a mesh containing:
first metal lines laterally extending along a first horizontal direction; and
second metal lines laterally extending along a second horizontal direction and adjoined to a respective subset of the first metal lines.

19. The method of claim 14 , further comprising:
forming a passivation dielectric layer over the first and the second metal lines and the backside bonding pads; and
forming openings through the passivation dielectric layer within areas of the backside bonding pads.

20. The method of claim 14 , wherein:
the memory die comprises a stepped dielectric material portion contacting stepped surfaces of the alternating stack and a connection via structure vertically extending through the stepped dielectric material portion; and
the method further comprises forming a contact via structure through the backside isolation dielectric layer

Assignees

• Sandisk Technologies Llc

Inventors

• Mizutani Yuki
• Higashitani Masaaki
• Kai James

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H10W80/211

  using auxiliary members, e.g. aids for protecting the bonding area · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title