Capping layer for improved deposition selectivity

Patent metadata

Field	Value
Publication number	US-10163794-B2
Application number	US-201615151616-A
Country	US
Kind code	B2
Filing date	May 11, 2016
Priority date	Jan 31, 2013
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

The present disclosure relates to an integrated chip having a back-end-of-the-line (BEOL) metal interconnect structure with capping layers that provide for improved reliability. In some embodiments, the integrated chip has a dielectric layer disposed over a semiconductor substrate, and one or more metal layer structures disposed within the dielectric layer. A first capping layer is located over the dielectric layer at positions between the one or more metal layer structures, so that the first capping layer is located along an interface having the one or more metal layer structures interspersed between the first capping layer. A second capping layer is located over the one or more metal layer structures. An etch stop layer is arranged over the first capping layer and the second capping layer and laterally surrounds the second capping layer.

First claim

What is claimed is:

1. An integrated chip, comprising:
a dielectric layer disposed over a semiconductor substrate;
a plurality of metal layer structures surrounded by the dielectric layer;
a first capping layer located over the dielectric layer at positions between the plurality of metal layer structures, wherein the first capping layer has bottom surfaces extending along a line along which the plurality of metal layer structures are interspersed between the first capping layer;
a second capping layer located over the plurality of metal layer structures;
an etch stop layer arranged over the first capping layer and the second capping layer and laterally surrounding the second capping layer, wherein the etch stop layer has a first thickness over the first capping layer and a second thickness over the second capping layer, wherein the first thickness is greater than the second thickness;
a second metal layer structure surrounded by a second dielectric layer over the etch stop layer, wherein the second metal layer structure extends through the etch stop layer and has a bottom surface physically contacting the second capping layer, and wherein the etch stop layer is arranged directly between the bottom surface of the second metal layer structure and a top of the first capping layer; and
wherein the bottom surface of the second metal layer structure that physically contacts the second capping layer laterally extends past an outermost sidewall of the second capping layer.

2. The integrated chip of claim 1 , wherein the etch stop layer contacts an upper surface of the first capping layer and an upper surface and sidewalls of the second capping layer.

3. The integrated chip of claim 1 , wherein the etch stop layer has a greater thickness than the second capping layer.

4. The integrated chip of claim 1 ,
wherein the second capping layer contacts the plurality of metal layer structures and the dielectric layer along a substantially planar interface; and
wherein the second capping layer has a first thickness in areas overlying the plurality of metal layer structures and a second non-zero thickness in areas not overlying the plurality of metal layer structures, wherein the first thickness is larger than the second non-zero thickness.

5. The integrated chip of claim 4 , wherein the second capping layer has vertical sidewalls that are laterally aligned with vertical sidewalls of the plurality of metal layer structures.

6. The integrated chip of claim 1 , wherein the etch stop layer has a substantially planar upper surface.

7. The integrated chip of claim 1 , wherein the second capping layer comprises cobalt.

8. The integrated chip of claim 1 , wherein the first capping layer comprises silicon nitride, silicon carbon-nitride, or silicon dioxide.

9. The integrated chip of claim 1 , wherein the first capping layer comprises an extreme low-k (ELK) film comprising silicon, carbon, and oxygen, wherein the ELK film has a greater density than the dielectric layer.

10. The integrated chip of claim 9 , wherein the ELK film comprises a dielectric constant having a value in a range of between approximately 2.8 and approximately 3.0 and a density in a range of between approximately 1.3 g/cm 3 and approximately 1.4 g/cm 3 .

11. The integrated chip of claim 1 , wherein the etch stop layer has sidewalls that physically contact opposing sidewalls of the second capping layer and a horizontally extending surface that physically contacts the bottom surface of the second metal layer structure.

12. An integrated chip, comprising:
a plurality of metal layer structures disposed within an extreme low-k (ELK) dielectric layer;
a first capping layer disposed over the ELK dielectric layer arranged along sidewalls of the plurality of metal layer structures;
a second capping layer disposed over the plurality of metal layer structures;
an etch stop layer disposed over the first capping layer and the second capping layer, wherein the etch stop layer has a first thickness over the first capping layer and a second thickness over the second capping layer, wherein the first thickness is greater than the second thickness; and
a second metal layer structure extending through the etch stop layer and having a bottom surface that directly contacts the second capping layer, wherein the etch stop layer vertically separates the bottom surface of the second metal layer structure that directly contacts the second capping layer from the first capping layer.

13. The integrated chip of claim 12 , wherein the etch stop layer comprises silicon nitride.

14. The integrated chip of claim 12 , wherein the second capping layer comprises cobalt.

15. The integrated chip of claim 12 , wherein the first capping layer consists of silicon nitride.

16. An integrated chip, comprising:
a dielectric layer disposed over a substrate;
a plurality of metal layer structures disposed within the dielectric layer;
a first capping layer located over the dielectric layer at positions between the plurality of metal layer structures, wherein the first capping layer has lower surfaces disposed along a line extending through sidewalls of the plurality of metal layer structures;
a second capping layer contacting upper surfaces of the plurality of metal layer structures, wherein the second capping layer has a first thickness in areas overlying the plurality of metal layer structures that is greater than a non-zero second thickness of the second capping layer in areas not overlying the plurality of metal layer structures, wherein the first thickness is larger than the second non-zero thickness;
an etch stop layer disposed over the first capping layer and the second capping layer, wherein the etch stop layer has a first thickness over the first capping layer and a second thickness over the second capping layer, wherein the first thickness is greater than the second thickness; and
a second metal layer structure having a horizontal surface physically contacting an upper surface of the second capping layer, wherein the etch stop layer vertically separates the horizontal surface of the second metal layer structure from the first capping layer.

17. The integrated chip of claim 16 , wherein the plurality of metal layer structures comprise copper.

18. The integrated chip of claim 16 , wherein the second metal layer structure is surrounded by a second dielectric layer over the etch stop layer.

19. The integrated chip of claim 1 , wherein the etch stop layer has a first height directly below the second metal layer structure and a second height outside of the second metal layer structure that is larger than the first height.

20. The integrated chip of claim 16 ,
wherein the etch stop layer has a first sidewall contacting a sidewall of the second capping layer and a second sidewall contact a sidewall of the second metal layer structure; and
wherein a top of the first sidewall is connected to a bottom of the second sidewall by way of a horizontally extending surface of the etch stop layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Chao-Chun
• Sung Su-Jen

Classifications

• H10W20/075

  of multilayered thin functional dielectric layers · CPC title

• H10W20/074 Primary

  of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers · CPC title

• H10W20/071

  of dielectric parts thereof · CPC title

• H10W20/48

  Insulating materials thereof · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title