Semiconductor device with a porous portion, wafer composite and method of manufacturing a semiconductor device

Patent metadata

Field	Value
Publication number	US-12412740-B2
Application number	US-202418407025-A
Country	US
Kind code	B2
Filing date	Jan 8, 2024
Priority date	Mar 6, 2019
Publication date	Sep 9, 2025
Grant date	Sep 9, 2025

Abstract

A semiconductor substrate includes a base portion, an auxiliary layer and a surface layer. The auxiliary layer is formed on the base portion. The surface layer is formed on the auxiliary layer. The surface layer is in contact with a first main surface of the semiconductor substrate. The auxiliary layer has a different electrochemical dissolution efficiency than the base portion and the surface layer. At least a portion of the auxiliary layer and at least a portion of the surface layer are converted into a porous structure. Subsequently, an epitaxial layer is formed on the first main surface.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a base portion, an auxiliary layer on the base portion, and a surface layer on the auxiliary layer;
forming pits in the surface layer; and
converting at least a portion of the auxiliary layer into a porous structure, wherein the porous structure comprises a layered portion formed at a distance to a first main surface of the semiconductor substrate, and wherein laterally separated columnar portions extend from the pits to the layered portion.

2. The method according to claim 1 , comprising:
forming, after the converting, an epitaxial layer on the first main surface.

3. The method according to claim 2 , comprising:
separating the epitaxial layer from the base portion along the layered portion.

4. The method according to claim 1 , wherein
forming pits in the surface layer is performed such that a vertical extension of the pits is in a range from 0.1 μm to 5 μm.

5. The method according to claim 1 , wherein
providing the semiconductor substrate is performed such that a vertical extension of the surface layer is in a range from 50 nm to 2 μm.

6. A method of manufacturing a semiconductor device, comprising:
forming a base portion;
forming a coarse-porous layered portion on the base portion, wherein a portion with a first porosity is on the coarse-porous layered portion;
forming a first fine-porous columnar portion, with a second porosity greater than the first porosity, on a first portion of the coarse-porous layered portion; and
forming a second fine-porous columnar portion, with a third porosity greater than the first porosity, on a second portion of the coarse-porous layered portion, wherein the portion on the coarse-porous layered portion is between the first fine-porous columnar portion and the second fine-porous columnar portion,
wherein an epitaxial layer is on the first fine-porous columnar portion, the portion on the coarse-porous layered portion and the second fine-porous columnar portion.

7. The method according to claim 6 , wherein
the first porosity of the portion on the coarse-porous layered portion is between zero and 10% of at least one of the second porosity of the first fine-porous columnar portion or the third porosity of the second fine-porous columnar portion.

8. The method according to claim 6 , wherein
forming the first fine-porous columnar portion is performed such that the first fine-porous columnar portion is in contact with a first surface of the portion on the coarse-porous layered portion.

9. The method according to claim 8 , wherein
forming the second fine-porous columnar portion is performed such that the second fine-porous columnar portion is in contact with a second surface of the portion on the coarse-porous layered portion.

10. The method according to claim 6 , wherein
forming the coarse-porous layered portion is performed such that the coarse-porous layered portion comprises a compound semiconductor.

11. The method according to claim 6 , wherein
forming the coarse-porous layered portion is performed such that the coarse-porous layered portion comprises at least one of gallium arsenide (GaAs), gallium nitride (GaN), silicon germanium (SiGe) or silicon carbide (SiC).

12. A method of manufacturing a semiconductor device, comprising:
forming a first fine-porous columnar portion, with a second porosity greater than a first porosity of a portion on a coarse-porous layered portion, on a first portion of the coarse-porous layered portion; and
forming a second fine-porous columnar portion, with a third porosity greater than the first porosity, on a second portion of the coarse-porous layered portion, wherein the portion on the coarse-porous layered portion is between the first fine-porous columnar portion and the second fine-porous columnar portion,
wherein an epitaxial layer is on the first fine-porous columnar portion, the portion on the coarse-porous layered portion and the second fine-porous columnar portion.

13. The method according to claim 12 , wherein
the first porosity of the portion on the coarse-porous layered portion is between zero and 10% of at least one of the second porosity of the first fine-porous columnar portion or the third porosity of the second fine-porous columnar portion.

14. The method according to claim 12 , wherein
forming the first fine-porous columnar portion is performed such that the first fine-porous columnar portion is in contact with a first surface of the portion on the coarse-porous layered portion.

15. The method according to claim 14 , wherein
forming the second fine-porous columnar portion is performed such that the second fine-porous columnar portion is in contact with a second surface of the portion on the coarse-porous layered portion.

16. The method according to claim 12 , comprising:
forming the coarse-porous layered portion such that the coarse-porous layered portion comprises a compound semiconductor.

17. The method according to claim 12 , comprising:
forming the coarse-porous layered portion such that the coarse-porous layered portion comprises gallium arsenide (GaAs).

18. The method according to claim 12 , comprising:
forming the coarse-porous layered portion such that the coarse-porous layered portion comprises gallium nitride (GaN).

19. The method according to claim 12 , comprising:
forming the coarse-porous layered portion such that the coarse-porous layered portion comprises silicon germanium (SiGe).

20. The method according to claim 12 , comprising:
forming the coarse-porous layered portion such that the coarse-porous layered portion comprises silicon carbide (SiC).

Assignees

• Infineon Technologies Ag

Inventors

• Moder Iris
• Goller Bernhard
• Hoechbauer Tobias Franz Wolfgang
• Rupp Roland
• Santos Rodriguez Francisco Javier
• Schulze Hans-Joachim

Classifications

• H10P90/15

  by making porous regions on the surface · CPC title

• H10P50/69

  using masks for semiconductor materials · CPC title

• H10P30/40

  into insulating materials · CPC title

• H10P14/6349

  Deposition of epitaxial materials · CPC title

• H10P14/2904

  Silicon carbide · CPC title