Semiconductor memory device having shield layer between peripheral circuit and cell array structures

Patent metadata

Field	Value
Publication number	US-12402301-B2
Application number	US-202217981719-A
Country	US
Kind code	B2
Filing date	Nov 7, 2022
Priority date	Apr 19, 2022
Publication date	Aug 26, 2025
Grant date	Aug 26, 2025

Abstract

Disclosed are semiconductor memory devices and their fabrication methods. The semiconductor memory device comprises a peripheral circuit structure including peripheral circuits on a semiconductor substrate and a first dielectric layer on the peripheral circuits, a cell array structure on the semiconductor substrate, and a shield layer between the peripheral circuit structure and the cell array structure. The cell array structure includes bit lines, first and second active patterns on the bit lines, first word lines that extend in a second direction on the first active patterns, second word lines that extend in the second direction on the second active patterns, data storage patterns on the first and second active patterns, and a second dielectric layer on the semiconductor substrate. A hydrogen concentration of the first dielectric layer is greater than that of the second dielectric layer.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a peripheral circuit structure including peripheral circuits on a semiconductor substrate and a first dielectric layer that covers the peripheral circuits;
a cell array structure on the semiconductor substrate; and
a shield layer between the peripheral circuit structure and the cell array structure,
wherein the cell array structure includes:
bit lines that extend lengthwise in a first direction on the semiconductor substrate;
first and second active patterns that are alternately disposed along the first direction on each of the bit lines, each of the first and second active patterns including a horizontal part and a vertical part, the first and second active patterns that are adjacent to each other being disposed symmetrically to each other;
first word lines that extend lengthwise in a second direction, cross the bit lines, and are disposed on the horizontal parts of the first active patterns;
second word lines that extend lengthwise in the second direction, cross the bit lines, and are disposed on the horizontal parts of the second active patterns;
data storage patterns on the first and second active patterns; and
a second dielectric layer on the semiconductor substrate, the second dielectric layer covering the bit lines, the first and second active patterns, the first and second word lines, and the data storage patterns, and

wherein a hydrogen concentration of the first dielectric layer is greater than a hydrogen concentration of the second dielectric layer.

2. The device of claim 1 , wherein the cell array structure is disposed on the peripheral circuit structure.

3. The device of claim 2 ,
wherein the shield layer has a cap shape that seals the peripheral circuit structure on the semiconductor substrate,
wherein on the semiconductor substrate, the shield layer surrounds the peripheral circuit structure when viewed in a plan view and downwardly covers the peripheral circuit structure, and
wherein the second dielectric layer covers the shield layer on the semiconductor substrate.

4. The device of claim 2 , further comprising:
inter-structure connection contacts that connect the peripheral circuits of the peripheral circuit structure to the bit lines of the cell array structure,
wherein the inter-structure connection contacts vertically penetrate the first dielectric layer, the second dielectric layer, and the shield layer.

5. The device of claim 4 , further comprising extension patterns disposed on the bit lines and electrically connecting the bit lines to the inter-structure connection contacts.

6. The device of claim 4 ,
wherein the inter-structure connection contacts include a barrier metal part adjacent to the shield layer, and
wherein a hydrogen diffusivity of the barrier metal part is less than a hydrogen diffusivity of the first dielectric layer.

7. The device of claim 2 ,
wherein the first dielectric layer covers the semiconductor substrate,
wherein the second dielectric layer covers the first dielectric layer, and
wherein the shield layer has a plate shape between the first dielectric layer and the second dielectric layer.

8. The device of claim 2 ,
wherein the shield layer has a box shape that seals the cell array structure on the semiconductor substrate,
wherein on the peripheral circuit structure, the shield layer surrounds the cell array structure when viewed in a plan view, upwardly supports the cell array structure, and downwardly covers the cell array structure, and
wherein the first dielectric layer buries the shield layer on the semiconductor substrate.

9. The device of claim 1 , wherein the shield layer includes aluminum oxide (Al 2 O 3 ) or metal nitride.

10. The device of claim 1 , wherein the cell array structure includes:
first gate dielectric patterns between the first active patterns and first sidewalls of the first word lines and between the first active patterns and bottom surfaces of the first word lines; and
second gate dielectric patterns between the second active patterns and second sidewalls of the second word lines and between the second active patterns and bottom surfaces of the second word lines.

11. The device of claim 1 , wherein the cell array structure further includes landing pads on the vertical parts of the first and second active patterns, the landing pads connecting the first and second active patterns to the data storage patterns.

12. The device of claim 1 ,
wherein the cell array structure is horizontally spaced apart from the peripheral circuit structure on the semiconductor substrate, and
wherein the shield layer has a partition shape between the cell array structure and the peripheral circuit structure on the semiconductor substrate.

13. The device of claim 12 ,
wherein the shield layer has a cap shape that seals the peripheral circuit structure on the semiconductor substrate, and
wherein the second dielectric layer covers the shield layer on the semiconductor substrate.

14. A semiconductor memory device, comprising:
a first circuit structure and a second circuit structure that are spaced apart from each other on a semiconductor substrate;
a shield layer that separates the first and second circuit structures from each other; and
a connection contact that penetrates the shield layer and connects the first and second circuit structures to each other,
wherein the first circuit structure includes a first transistor and a first dielectric layer that covers the first transistor,
wherein the second circuit structure includes a second transistor and a second dielectric layer that covers the second transistor,
wherein the second transistor includes:
a bit line that extends lengthwise in a first direction on the semiconductor substrate;
first and second active patterns that are disposed along the first direction on the bit line;
first word lines that extend lengthwise in a second direction, cross the bit line, and are disposed on the first active patterns; and
second word lines that extend lengthwise in the second direction, cross the bit line, and are disposed on the second active patterns, and

wherein a hydrogen diffusivity of the shield layer is less than a hydrogen diffusivity of the first dielectric layer and a hydrogen diffusivity of the second dielectric layer.

15. The device of claim 14 ,
wherein the second circuit structure is disposed on the first circuit structure,
wherein the shield layer has a cap shape that seals the first circuit structure on the semiconductor substrate,
wherein on the semiconductor substrate, the shield layer surrounds the first circuit structure when viewed in a plan view and downwardly covers the first circuit structure, and
wherein the second dielectric layer covers the shield layer on the semiconductor substrate.

16. The device of claim 14 ,
wherein the first circuit structure and the second circuit structure are horizontally spaced apart from each other on the semiconductor substrate, and
wherein the shield layer has a partition shape that crosses between the first circuit structure and the second circuit structure on the semiconductor substrate.

17. The device of claim 14 ,
wherein the second circuit structure is disposed on the first circuit structure,
wherein the shield layer has a box shape that seals the second circuit structure on the semiconductor substrate,
wherein on the first circuit structure, the shield layer surrounds the second circuit structure when viewed in a plan view, upwardly supports the second circuit structure, and downwardly cove

Assignees

• Samsung Electronics Co Ltd

Inventors

• Cho Min Hee
• Ryu Min Tae
• Ryu Huije
• Yoo Sungwon
• Lee Yongjin
• Lee Wonsok

Classifications

• H10B12/488

  Word lines · CPC title

• H10B12/485

  Bit line contacts · CPC title

• H10B12/482

  Bit lines · CPC title

• H10B12/50

  Peripheral circuit region structures · CPC title

• H10B12/05

  Making the transistor · CPC title