Three-dimensional semiconductor memory device

Patent metadata

Field	Value
Publication number	US-11410951-B2
Application number	US-202117207242-A
Country	US
Kind code	B2
Filing date	Mar 19, 2021
Priority date	Aug 25, 2020
Publication date	Aug 9, 2022
Grant date	Aug 9, 2022

Abstract

A three-dimensional semiconductor memory device is provided. The device may include a first substrate including a bit-line connection region and a word-line connection region, a cell array structure on the first substrate, a second substrate including a first core region and a second core region, which are respectively overlapped with the bit-line connection region and the word-line connection region, and a peripheral circuit structure on the second substrate.

First claim

What is claimed is:

1. A three-dimensional semiconductor memory device comprising:
a first substrate including a bit-line connection region and a word-line connection region;
a cell array structure on the first substrate,
a second substrate including a first core region and a second core region, which are respectively overlapped with the bit-line connection region and the word-line connection region; and
a peripheral circuit structure on the second substrate,
wherein the cell array structure comprises:
word lines stacked on the first substrate;
bit lines crossing the word lines in a first direction perpendicular to a top surface of the first substrate;
first lower metal pads provided on the bit-line connection region and connected to the bit lines; and
second lower metal pads provided on the word-line connection region and connected to the word lines;
wherein the peripheral circuit structure comprises:
sense amplifiers provided on the first core region;
sub-word line drivers provided on the second core region;
first upper metal pads provided on the first core region and connected to the sense amplifiers; and
second upper metal pads provided on the second core region and connected to the sub-word line drivers,
wherein the first lower metal pads are bonded to the first upper metal pads, and
the second lower metal pads are bonded to the second upper metal pads.

2. The three-dimensional semiconductor memory device of claim 1 , wherein the cell array structure further comprises memory cells, which are respectively provided at intersections of the word lines and the bit lines,
each of the memory cells comprises a cell transistor and a capacitor, which is connected to an end of the cell transistor,
the cell transistor comprises a semiconductor pattern parallel to the top surface of the first substrate, and
the capacitor is connected to an end of the semiconductor pattern and comprises a storage electrode parallel to the top surface of the first substrate.

3. The three-dimensional semiconductor memory device of claim 1 , wherein the word lines are extended in a second direction parallel to the top surface of the first substrate, and
the bit lines are arranged to be spaced apart from each other in the second direction and a third direction crossing the first direction and the second direction.

4. The three-dimensional semiconductor memory device of claim 3 , wherein the cell array structure further comprises bit-line connection lines provided between the bit lines and the first lower metal pads, when viewed in a vertical view,
the bit-line connection lines are extended in the third direction and are parallel to each other, and
each of the bit-line connection lines is connected the bit lines arranged in the third direction.

5. The three-dimensional semiconductor memory device of claim 4 , wherein each of the first lower metal pads is overlapped with at least two of the bit-line connection lines, when viewed in a plan view.

6. The three-dimensional semiconductor memory device of claim 4 , wherein the cell array structure further comprises landing conductive patterns provided between the bit-line connection lines and the first lower metal pads, when viewed in the vertical view, and
the landing conductive patterns are extended in the first direction to cross at least two of the bit-line connection lines.

7. The three-dimensional semiconductor memory device of claim 6 , wherein each of the landing conductive patterns is connected to a corresponding one of the bit-line connection lines.

8. The three-dimensional semiconductor memory device of claim 6 , wherein, when measured in the first direction, each of the first lower metal pads has a first width and each of the landing conductive patterns has a second width, and the first width is larger than the second width.

9. The three-dimensional semiconductor memory device of claim 1 , wherein the word lines are extended in a second direction parallel to the top surface of the first substrate,
each of the word lines has a word-line pad on the word-line connection region,
the plurality of word-line pads are stacked to form a staircase structure on the word-line connection region, and
the second lower metal pads are connected to the plurality of word-line pads.

10. The three-dimensional semiconductor memory device of claim 9 , wherein word-line pads, which are located at a same level from the first substrate from among the plurality of word-line pads, are spaced apart from each other in a third direction crossing the second direction, and
when measured in the third direction, each of the plurality of word-line pads has a first width and each of the second lower metal pads has a second width, which is larger than the first width.

11. A three-dimensional semiconductor memory device comprising:
a first substrate including a bit-line connection region, a word-line connection region, and a first peripheral region;
a cell array structure including a memory cell array, which includes memory cells three-dimensionally arranged on the bit-line connection region and the word-line connection region of the first substrate, and the cell array structure including lower control circuits, which are provided on the first peripheral region of the first substrate;
a second substrate including a first core region, a second core region, and a second peripheral region, which are overlapped with the bit-line connection region, the word-line connection region, and the first peripheral region, respectively; and
a peripheral circuit structure including sense amplifiers provided on the first core region of the second substrate, sub-word line drivers provided on the second core region of the second substrate, and upper control circuits provided on the second peripheral region of the second substrate.

12. The three-dimensional semiconductor memory device of claim 11 , wherein the cell array structure comprises lower metal pads and the peripheral circuit structure comprises upper metal pads, and the cell array structure is bonded to the peripheral circuit structure by bonding between the lower metal pads and the upper metal pads.

13. The three-dimensional semiconductor memory device of claim 11 , wherein the cell array structure comprises first lower metal pads connected to bit lines of the memory cell array, second lower metal pads connected to word lines of the memory cell array, and third lower metal pads connected to the lower control circuits,
the peripheral circuit structure comprises first upper metal pads connected to the sense amplifiers, second upper metal pads connected to the sub-word line drivers, and third upper metal pads connected to the upper control circuits, and
the first lower metal pads, the second lower metal pads, and the third lower metal pads are bonded to the first upper metal pads, the second upper metal pads, and the third upper metal pads, respectively.

14. The three-dimensional semiconductor memory device of claim 11 , wherein at least one of the upper control circuits and the lower control circuits comprises a power capacitor.

15. The three-dimensional semiconductor memory device of claim 11 , further comprising:
a penetration plug that penetrates the first substrate, on the first peripheral region; and
an input/output pad disposed on an outside surface of the first substrate and coupled to the penetration plug.

16. The three-dimensional semiconductor memory device of claim 11 , further comprising:
a penetration plug that penetrates the second substrate, on the second peripheral region; and
an input/output pad disposed

Assignees

• Samsung Electronics Co Ltd

Inventors

• Choi Hyungeun
• Kim Eun-Ji
• Moon Jong-Ho
• Mun Hyoungyol
• Yoo Han-Sik
• Lee Kiseok
• Jung Seungjae
• An Taehyun
• Han Sangyeon
• Hwang Yoosang

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• G11C11/4085 Primary

  Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge · CPC title