Semiconductor package

Patent metadata

Field	Value
Publication number	US-12400980-B2
Application number	US-202318508807-A
Country	US
Kind code	B2
Filing date	Nov 14, 2023
Priority date	Sep 22, 2020
Publication date	Aug 26, 2025
Grant date	Aug 26, 2025

Abstract

A semiconductor package includes a sequential stack of first and second semiconductor chips, and a first internal connection member that connects the first and second semiconductor chips to each other. The first semiconductor chip includes a first substrate that has a first top surface and a first bottom surface that are opposite to each other, and a first conductive pad on the first top surface. The second semiconductor chip includes a second substrate that has a second top surface and a second bottom surface that are opposite to each other, and a second conductive bump on the second bottom surface. The first internal connection member connects the first conductive pad to the second conductive bump. The first conductive pad has a first width in one direction. The second conductive bump has a second width in the one direction. The first width is smaller than the second width.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a first redistribution substrate;
a first semiconductor device mounted through a first internal connection member on the first redistribution substrate; and
a first mold layer that covers the first semiconductor device and the first redistribution substrate,
wherein the first redistribution substrate includes
a plurality of dielectric layers,
a plurality of redistribution patterns penetrating at least one of the plurality of dielectric layers, and
a first conductive pad above the plurality of redistribution patterns,

wherein the first semiconductor device includes a conductive bump that protrudes outwardly from a bottom surface of the first semiconductor device,
wherein the first internal connection member connects the first conductive pad to the conductive bump,
wherein a width of the first conductive pad is smaller than a width of the conductive bump, and
wherein the first internal connection member is between the first conductive pad and the conductive bump.

2. The semiconductor package of claim 1 , wherein the first redistribution substrate includes:
a first dielectric layer,
an under-bump in the first dielectric layer,
a second dielectric layer that covers the first dielectric layer,
a first redistribution pattern that includes a first via part and a first line part, the first via part penetrating the second dielectric layer and having a connection with the under-bump, and the first line part protruding onto the second dielectric layer,
a third dielectric layer that covers the first redistribution pattern and the second dielectric layer,
a second redistribution pattern that includes a second via part and a second line part, the second via part penetrating the third dielectric layer and having a connection with the first redistribution pattern, and the second line part protruding onto the third dielectric layer,
a fourth dielectric layer that covers the second redistribution pattern and the third dielectric layer, and
a third redistribution pattern that that includes a third via part and a first pad part, the third via part penetrating the fourth dielectric layer.

3. The semiconductor package of claim 2 , wherein the first conductive pad is disposed on the third redistribution pattern.

4. The semiconductor package of claim 1 , further comprising:
an under-fill layer between the first redistribution substrate and the first semiconductor device,
wherein the under-fill layer is in contact with a sidewall of the first conductive pad.

5. The semiconductor package of claim 1 , wherein the width of the first conductive pad is about 0.8 to 0.9 times the width of the conductive bump.

6. The semiconductor package of claim 1 , wherein the first internal connection member includes:
a first connection region adjacent to the first conductive pad; and
a second connection region adjacent to the conductive bump,
wherein each of the first connection region and the second connection region includes gold (Au), and
wherein an average thickness of the first connection region is smaller than an average thickness of the second connection region.

7. The semiconductor package of claim 1 , further comprising:
a second redistribution substrate on the first mold layer;
an upper semiconductor package mounted on the second redistribution substrate;
a second internal connection member that connects the second redistribution substrate to the upper semiconductor package; and
a mold via that penetrates the first mold layer and connects the first redistribution substrate to the second redistribution substrate.

8. The semiconductor package of claim 1 , further comprising:
a second redistribution substrate on the first mold layer;
a connection substrate between the first redistribution substrate and the second redistribution substrate and covered with the first mold layer, the connection substrate including a cavity into which the first semiconductor device is inserted;
an upper semiconductor package mounted on the second redistribution substrate; and
a second internal connection member that connects the second redistribution substrate to the upper semiconductor package.

9. The semiconductor package of claim 7 , wherein the second redistribution substrate includes:
a fifth dielectric layer;
a fourth redistribution pattern that includes a fourth via part and a third line part, the fourth via part penetrating the fifth dielectric layer and having a connection with the mold via, and the third line part protruding onto the fifth dielectric layer;
a sixth dielectric layer that covers the fifth dielectric layer and the fourth redistribution pattern;
a fifth redistribution pattern that includes a fifth via part and a fourth line part, the fifth via part penetrating the sixth dielectric layer and having a connection with the fourth redistribution pattern, and the fourth line part protruding onto the sixth dielectric layer;
a seventh dielectric layer that covers the sixth dielectric layer and the fifth redistribution pattern;
a sixth redistribution pattern that that includes a sixth via part and a second pad part, the sixth via part penetrating the seventh dielectric layer; and
a second conductive pad on the sixth redistribution pattern,
wherein the upper semiconductor package includes a package substrate and a second semiconductor device mounted on the package substrate, the package substrate including a substrate pad on a bottom surface of the package substrate,
wherein a width of the second conductive pad is smaller than a width of the substrate pad.

10. A semiconductor package, comprising:
a first semiconductor package;
a second semiconductor package on the first semiconductor package; and
a first internal connection member between the first semiconductor package and the second semiconductor package,
wherein the first semiconductor package includes
a first redistribution substrate,
a first semiconductor device mounted through a second internal connection member on the first redistribution substrate,
a first mold layer that covers the first semiconductor device and the first redistribution substrate,
a second redistribution substrate on the first mold layer, and
a first conductive pad on the second redistribution substrate,

wherein the second semiconductor package includes
a package substrate including an upper substrate pad and a lower substrate pad,
a second semiconductor device connected to the package substrate, and
a second molding covering the second semiconductor device,

wherein the first internal connection member is in contact with the first conductive pad of the first semiconductor package and the lower substrate pad of the second semiconductor package,
wherein a width of the first conductive pad is smaller than a width of the lower substrate pad, and
wherein the width of the first conductive pad is smaller than or same as a maximum width of the first internal connection member.

11. The semiconductor package of claim 10 , further comprising:
a mold via that penetrates the first mold layer and connects the first redistribution substrate to the second redistribution substrate.

12. The semiconductor package of claim 10 , further comprising:
a wire connecting the package substrate and the second semiconductor device.

13. The semiconductor package of claim 10 , further comprising:
an under-fill layer between the first semiconductor package and the second semiconductor package,
wherein the under-fill layer is in contact with a sidewall of the first conductive pad.

14. The semiconductor package of claim 10 , f

Assignees

• Samsung Electronics Co Ltd

Inventors

• Seo Sunkyoung
• Lee Teak Hoon
• Jo Chajea

Classifications

• H10W72/5522

  comprising gold [Au] · CPC title

• H10W20/0249

  wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture · CPC title

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title