Semiconductor package

Patent metadata

Field	Value
Publication number	US-10083939-B2
Application number	US-201715421386-A
Country	US
Kind code	B2
Filing date	Jan 31, 2017
Priority date	May 17, 2016
Publication date	Sep 25, 2018
Grant date	Sep 25, 2018

Abstract

A semiconductor package includes: a first semiconductor chip in which a through-electrode is provided; a second semiconductor chip connected to a top surface of the first semiconductor chip; a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer; and a second connection bump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.

First claim

What is claimed is:

1. A semiconductor package comprising:
a first semiconductor chip that includes a first through-electrode;
a plurality of second semiconductor chips stacked on a top surface of the first semiconductor chip, at least one of the plurality of second semiconductor chips including a second through-electrode;
a plurality of first connection bumps attached to a bottom surface of the first semiconductor chip, each of the plurality of first connection bumps comprising a first pillar structure and a first solder layer; and
a plurality of second connection bumps located between the first semiconductor chip and a lowermost second semiconductor chip and between adjacent two second semiconductor chips among the plurality of second semiconductor chips, each of the plurality of second connection bumps comprising a second pillar structure and a second solder layer,
wherein the first pillar structure comprises a first pillar layer and a diffusion barrier layer sequentially stacked on the bottom surface of the first semiconductor chip, the first pillar layer comprises a material that is different from a material of the second pillar structure.

2. The semiconductor package of claim 1 ,
wherein
the first pillar layer located on the bottom surface of the first semiconductor chip; and
the diffusion barrier layer located on the first pillar layer farther from the bottom surface of the first semiconductor chip than the first pillar layer is located from the bottom surface of the first semiconductor chip.

3. The semiconductor package of claim 2 ,
wherein the first pillar layer of the first pillar structure comprises a material having a Young's modulus that is lower than a Young's modulus of a material included in the second pillar structure.

4. The semiconductor package of claim 2 ,
wherein the first pillar structure comprises copper (Cu) and the second pillar structure comprises nickel (Ni).

5. The semiconductor package of claim 2 ,
wherein the first pillar layer of the first pillar structure comprises Cu and the diffusion barrier layer comprises Ni.

6. The semiconductor package of claim 2 ,
wherein the first pillar structure further comprises an adhesive layer formed on the diffusion barrier layer and comprises Cu.

7. The semiconductor package of claim 1 ,
wherein the first through-electrode is connected to at least one of the plurality of first connection bumps or the plurality of second connection bumps.

8. The semiconductor package of claim 1 , further comprising a first molding member that surrounds side surfaces of the plurality of second semiconductor chips and the plurality of second connection bumps and does not contact the bottom surface of the first semiconductor chip or the plurality of first connection bumps.

9. The semiconductor package of claim 1 ,
wherein a first height of the first pillar structure in a first direction that is perpendicular to the top surface of the first semiconductor chip is greater than a second height of the second pillar structure in the first direction.

10. The semiconductor package of claim 1 ,
wherein the second solder layer comprises a material having a melting point higher than a melting point of the first solder layer.

11. The semiconductor package of claim 1 , further comprising:
a substrate facing the bottom surface of the first semiconductor chip and electrically connected to the first semiconductor chip through the plurality of first connection bumps; and
an external connection terminal located on a bottom surface of the substrate opposite to a top surface of the substrate that faces the first semiconductor chip,
wherein a width of one of the plurality of first connection bumps in a second direction that is parallel to the top surface of the first semiconductor chip is smaller than a width of the external connection terminal in the second direction.

12. The semiconductor package of claim 11 ,
wherein the substrate is an interposer or a printed circuit board (PCB),
wherein the width of the external connection terminal in the second direction is greater than 50 μm.

13. The semiconductor package of claim 11 , further comprising:
a first molding member that surrounds side surfaces of the plurality of second semiconductor chips and the plurality of second connection bumps and does not contact the bottom surface of the first semiconductor chip or the plurality of first connection bumps; and
a second molding member located between the substrate and the bottom surface of the first semiconductor chip and surrounds the plurality of first connection bumps.

14. A semiconductor package comprising:
a substrate;
a first semiconductor chip mounted on a top surface of the substrate and comprising a through-electrode provided therein;
a second semiconductor chip mounted on a top surface of the first semiconductor chip and comprising a through-electrode provided therein;
a third semiconductor chip mounted on a top surface of the second semiconductor chip;
a plurality of first connection bumps located between the first semiconductor chip and the substrate, each of the plurality of first connection bumps comprising a first pillar structure and a first solder layer; and
a plurality of second connection bumps located between the first semiconductor chip and the second semiconductor chip and between the second semiconductor chip and the third semiconductor chip, each of the plurality of second connection bumps comprising a second pillar structure and a second solder layer,
wherein the first pillar structure comprises a material that is different from a material of the second pillar structure.

15. The semiconductor package of claim 14 ,
wherein the first pillar structure comprises a material having a Young's modulus lower than a Young's modulus of a material included in the second pillar structure.

16. The semiconductor package of claim 14 , further comprising an external connection terminal located on a bottom surface of the substrate and comprising an under-bump metal (UBM) layer and a solder ball, which are sequentially located on the bottom surface of the substrate.

17. The semiconductor package of claim 14 ,
wherein the first pillar structure comprises:
a first pillar layer located on a bottom surface of the first semiconductor chip; and
a diffusion barrier layer located on the first pillar layer farther from the bottom surface of the first semiconductor chip than the first pillar layer is located from the bottom surface of the first semiconductor chip, the diffusion barrier layer contacting the first solder layer.

18. A semiconductor package, comprising:
a first semiconductor chip;
a plurality of first connection bumps attached to a bottom surface of the first semiconductor chip, each of the plurality of first connection bumps comprising a first pillar structure and a first solder layer, the first pillar structure comprising a first material having a first Young's modulus;
a plurality of second semiconductor chips stacked on a top surface of the first semiconductor chip; and
a plurality of second connection bumps located between the first semiconductor chip and a lowermost second semiconductor chip and between adjacent two second semiconductor chips among the plurality of second semiconductor chips, each of the plurality of second connection bumps comprising a second pillar structure and a second solder layer, the second pillar structure comprising a second material having a second Young's modulus, the second Young's modulus being greater than the first Young's modulus.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Seo Sun-Kyoung
• Jo Cha-Jea
• Ha Soo-Hyun

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title