Semiconductor package and semiconductor device including the same

Patent metadata

Field	Value
Publication number	US-10658300-B2
Application number	US-201816102391-A
Country	US
Kind code	B2
Filing date	Aug 13, 2018
Priority date	Jan 17, 2018
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

A semiconductor package includes a lower chip, an upper chip on the lower chip, and an adhesive layer between the lower chip and the upper chip. The lower chip has first through silicon vias (TSVs) and pads on an upper surface thereof. The pads are connected to the first TSVs, respectively. The upper chip includes bumps on a lower surface thereof. The bumps are bonded to the pads. Vertical centerlines of the bumps are aligned with vertical centerlines of the first TSVs, respectively. The vertical centerlines of the bumps are offset from the vertical centerlines of the pads, respectively, in a peripheral region of the lower chip.

First claim

What is claimed is:

1. A semiconductor comprising:
a lower chip including a lower chip body, first through silicon vias (TSVs) extending vertically through the lower chip body, and pads on an upper surface of the lower chip body, the pads being electrically connected to the first TSVs, respectively;
an upper chip on the lower chip, the upper chip including an upper chip body, and bumps on a lower surface of the upper chip body, the bumps directly bonded to corresponding ones of the pads of the lower chip, respectively, and each of the bumps including a pillar and a solder layer; and
an adhesive layer between the lower chip body and the upper chip body,
wherein each of the pillars of the bumps, the first TSVs and the pads has a centerline extending in a direction perpendicular to the upper surface of the lower chip body,
wherein the centerlines of the pillars of the bumps extend through geometric centers of the pillars, respectively, as viewed in a plan view of the semiconductor package,
wherein the centerlines of the first TSVs extend through axial centers of the first TSVs, respectively, the centerlines of the pads extend vertically through geometric centers of the pads, respectively, as viewed in a plan view of the semiconductor package,
wherein the centerlines of the pillars of the bumps are aligned with the centerlines of the first TSVs, respectively, in a peripheral region of the lower chip, the centerline of the pillar of a first bump from among the bumps is offset from the centerline of a corresponding pad from among the pads to which the first bump is bonded, and
wherein a misaligned extent of each pad from among the pads is a distance between the centerline of a pillar of a bump from among the bumps bonded to the pad and the centerline of the pad, divided by a width of the pillar of the bump bonded to the pad, and the misaligned extent for each of the pads is less than 50%;
wherein in a central region of the lower chip, the centerline of the pillar of a second bump from among the bumps and the centerline of a corresponding pad from among the pads to which the second bump is bonded are aligned with each other, and
wherein in the peripheral region of the lower chip, distances by which the centerlines of the pillars of a first plurality of bumps from among the bumps and the centerlines of a corresponding first plurality of pads from among the pads to which the first plurality of bumps are bonded are offset vary among the first plurality of bumps and the corresponding first plurality of pads bonded to each other.

2. The semiconductor package according to claim 1 , wherein the pads are disposed symmetrically about a center of the lower chip, as viewed in a plan view of the semiconductor package.

3. The semiconductor package according to claim 1 , wherein the solder layers of each of the bumps cover an upper surface of each of the pads.

4. The semiconductor package according to claim 1 , wherein a diameter of each of the first TSVs is less than a width of each of the pads,
in the central region of the lower chip, a first one of the pads is disposed symmetrically about the centerline of a first TSV from among the first TSVs electrically connected thereto, and
in the peripheral region of the lower chip, a second one of the pads is disposed asymmetrically with respect to the centerline of a first TSV from among the first TSVs electrically connected thereto.

5. The semiconductor package according to claim 1 , wherein the upper chip includes second TSVs extending vertically in the upper chip body, and
wherein the second TSVs are electrically connected to the bumps, respectively.

6. The semiconductor package according to claim 5 , wherein the second TSVs have centerlines extending through axial centers of the second TSVs, respectively, and the centerlines of the second TSVs are aligned with the centerlines of the pillars of the bumps, respectively.

7. The semiconductor package according to claim 1 , wherein the lower chip is of a different type than the upper chip and has a different size than the upper chip.

8. The semiconductor package according to claim 1 , wherein the semiconductor package is a high bandwidth memory (HBM) package.

9. The semiconductor package according to claim 1 , wherein the adhesive layer is a non-conductive film (NCF) on a lower surface of the upper chip body and surrounding the bumps.

10. The semiconductor package according to claim 1 , wherein the lower chip is a buffer chip and the upper chip is a memory chip.

11. The semiconductor package according to claim 10 , further comprising a second memory chip on the upper chip,
wherein the semiconductor package is a high bandwidth memory (HBM) package,
the upper chip has second TSVs extending vertically through the upper chip body, and second pads disposed on the upper chip body and directly electrically connected to the second TSVs, respectively, and
the second TSVs having centerlines extending through axial centers of the second TSVs, respectively,
the second pads have centerlines extending vertically through geometric centers of the second pads, respectively, as viewed in a plan view of the semiconductor package,
the centerlines of the second TSVs are aligned with the centerlines of the pillars of the bumps, respectively, and
in a peripheral region of the memory chip, the centerline of each of the second TSVs is offset from the centerline of the second pad to which the second TSV is directly electrically connected.

12. A semiconductor device comprising the semiconductor package as claimed in claim 11 , further comprising:
a printed circuit board (PCB);
an interposer mounted on the PCB, the semiconductor package being mounted on the interposer; and
a processor chip mounted on the interposer as laterally spaced apart from the HBM package.

13. A semiconductor package comprising:
a lower chip including a lower chip body, first through silicon vias (TSVs) extending vertically through the lower chip body, and pads on an upper surface of the lower chip body, the pads being electrically connected to the first TSVs, respectively;
an upper chip on the lower chip, the upper chip including an upper chip body, and bumps on a lower surface of the upper chip body, the bumps directly bonded to corresponding ones of the pads of the lower chip, respectively, and each of the bumps including a pillar and a solder layer; and
an adhesive layer between the lower chip body and the upper chip body,
wherein each of the pillars of the bumps, the first TSVs and the pads has a centerline extending in a direction perpendicular to the upper surface of the lower chip body,
wherein the centerlines of the pillars of the bumps extend through geometric centers of the pillars, respectively, as viewed in a plan view of the semiconductor package,
wherein the centerlines of the first TSVs extend through axial centers of the first TSVs, respectively, wherein the centerlines of the pads extend vertically through geometric centers of the pads, respectively, as viewed in a plan view of the semiconductor package,
wherein the centerlines of the pillars of the bumps are aligned with the centerlines of the first TSVs, respectively, in a peripheral region of the lower chip, the centerline of the pillar of a first bump from among the bumps is offset from the centerline of a corresponding first pad from among the pads to which the first bump is bonded,
wherein a misaligned extent of each pad from among the pads is a distance between the centerline of a pillar of a bump from among the bumps bonded to the pad and the centerline of the pad, divided by a width of the pillar of the bump bonded to the pad, and

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Young-Lyong
• Baek Seung-Duk

Classifications

• H05K1/111

  Pads for surface mounting, e.g. lay-out · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H01L25/0657

  Electricity · mapped topic

• H01L2225/06513

  Electricity · mapped topic

• H01L25/50

  Electricity · mapped topic